LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke lc_ctrl_smoke 0 50 0.00
V1 csr_hw_reset lc_ctrl_csr_hw_reset 1.140s 325.076us 5 5 100.00
V1 csr_rw lc_ctrl_csr_rw 1.110s 52.413us 20 20 100.00
V1 csr_bit_bash lc_ctrl_csr_bit_bash 2.640s 128.037us 5 5 100.00
V1 csr_aliasing lc_ctrl_csr_aliasing 1.690s 33.963us 5 5 100.00
V1 csr_mem_rw_with_rand_reset lc_ctrl_csr_mem_rw_with_rand_reset 1.840s 30.954us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr lc_ctrl_csr_rw 1.110s 52.413us 20 20 100.00
lc_ctrl_csr_aliasing 1.690s 33.963us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 state_post_trans lc_ctrl_state_post_trans 0 50 0.00
V2 regwen_during_op lc_ctrl_regwen_during_op 0 10 0.00
V2 rand_wr_claim_transition_if lc_ctrl_claim_transition_if 0 10 0.00
V2 lc_prog_failure lc_ctrl_prog_failure 0 50 0.00
V2 lc_state_failure lc_ctrl_state_failure 0 50 0.00
V2 lc_errors lc_ctrl_errors 0 50 0.00
V2 security_escalation lc_ctrl_state_failure 0 50 0.00
lc_ctrl_prog_failure 0 50 0.00
lc_ctrl_errors 0 50 0.00
lc_ctrl_security_escalation 0 50 0.00
lc_ctrl_jtag_state_failure 0 20 0.00
lc_ctrl_jtag_prog_failure 0 20 0.00
lc_ctrl_jtag_errors 0 20 0.00
V2 jtag_access lc_ctrl_jtag_smoke 0 20 0.00
lc_ctrl_jtag_state_post_trans 0 20 0.00
lc_ctrl_jtag_prog_failure 0 20 0.00
lc_ctrl_jtag_errors 0 20 0.00
lc_ctrl_jtag_access 0 50 0.00
lc_ctrl_jtag_regwen_during_op 0 10 0.00
lc_ctrl_jtag_csr_hw_reset 5.770s 725.922us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.210s 390.918us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 21.100s 1.755ms 10 10 100.00
lc_ctrl_jtag_csr_aliasing 15.120s 1.412ms 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.940s 145.571us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.350s 146.417us 10 10 100.00
lc_ctrl_jtag_alert_test 1.900s 58.353us 10 10 100.00
V2 jtag_priority lc_ctrl_jtag_priority 0 10 0.00
V2 lc_ctrl_volatile_unlock lc_ctrl_volatile_unlock_smoke 0 50 0.00
V2 stress_all lc_ctrl_stress_all 0 50 0.00
V2 alert_test lc_ctrl_alert_test 0 50 0.00
V2 tl_d_oob_addr_access lc_ctrl_tl_errors 5.210s 553.891us 20 20 100.00
V2 tl_d_illegal_access lc_ctrl_tl_errors 5.210s 553.891us 20 20 100.00
V2 tl_d_outstanding_access lc_ctrl_csr_hw_reset 1.140s 325.076us 5 5 100.00
lc_ctrl_csr_rw 1.110s 52.413us 20 20 100.00
lc_ctrl_csr_aliasing 1.690s 33.963us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.040s 39.879us 20 20 100.00
V2 tl_d_partial_access lc_ctrl_csr_hw_reset 1.140s 325.076us 5 5 100.00
lc_ctrl_csr_rw 1.110s 52.413us 20 20 100.00
lc_ctrl_csr_aliasing 1.690s 33.963us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.040s 39.879us 20 20 100.00
V2 TOTAL 110 700 15.71
V2S tl_intg_err lc_ctrl_sec_cm 0 5 0.00
lc_ctrl_tl_intg_err 4.170s 112.030us 20 20 100.00
V2S sec_cm_bus_integrity lc_ctrl_tl_intg_err 4.170s 112.030us 20 20 100.00
V2S sec_cm_transition_config_regwen lc_ctrl_regwen_during_op 0 10 0.00
V2S sec_cm_manuf_state_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_transition_ctr_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_manuf_state_bkgn_chk lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_transition_ctr_bkgn_chk lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_state_config_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_kmac_fsm_sparse lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_local_esc lc_ctrl_state_failure 0 50 0.00
lc_ctrl_sec_cm 0 5 0.00
V2S sec_cm_main_fsm_global_esc lc_ctrl_security_escalation 0 50 0.00
V2S sec_cm_main_ctrl_flow_consistency lc_ctrl_state_post_trans 0 50 0.00
lc_ctrl_jtag_state_post_trans 0 20 0.00
V2S sec_cm_intersig_mubi lc_ctrl_sec_mubi 0 50 0.00
V2S sec_cm_token_valid_ctrl_mubi lc_ctrl_sec_mubi 0 50 0.00
V2S sec_cm_token_digest lc_ctrl_sec_token_digest 0 50 0.00
V2S sec_cm_token_mux_ctrl_redun lc_ctrl_sec_token_mux 0 50 0.00
V2S sec_cm_token_valid_mux_redun lc_ctrl_sec_token_mux 0 50 0.00
V2S TOTAL 20 175 11.43
V3 stress_all_with_rand_reset lc_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 185 1030 17.96

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 27 27 9 33.33
V2S 5 5 1 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.31 97.82 96.40 95.74 97.62 98.52 99.00 96.07

Failure Buckets

Past Results