LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.150s	221.311us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.090s	25.541us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.080s	17.453us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.910s	125.328us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.630s	71.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	4.950s	245.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.080s	17.453us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	71.720us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.550s	403.681us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.140s	1.412ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	12.504us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.520s	427.315us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.500s	1.762ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_prog_failure	4.520s	427.315us	50	50	100.00
		lc_ctrl_errors	18.500s	1.762ms	50	50	100.00
		lc_ctrl_security_escalation	20.120s	641.903us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.339m	2.767ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.000s	3.892ms	20	20	100.00
		lc_ctrl_jtag_errors	2.182m	19.482ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.660s	926.761us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.230s	4.006ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.000s	3.892ms	20	20	100.00
		lc_ctrl_jtag_errors	2.182m	19.482ms	20	20	100.00
		lc_ctrl_jtag_access	19.540s	3.169ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.570s	1.175ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.510s	122.266us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.200s	671.540us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.740s	2.542ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.800s	12.039ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.950s	150.845us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.910s	190.467us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.910s	690.610us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.110s	1.054ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	5.683m	10.002ms	37	50	74.00
V2	stress_all	lc_ctrl_stress_all	12.691m	114.156ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.240s	22.439us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.920s	598.086us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.920s	598.086us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.090s	25.541us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	17.453us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	71.720us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	158.586us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.090s	25.541us	5	5	100.00
		lc_ctrl_csr_rw	1.080s	17.453us	20	20	100.00
		lc_ctrl_csr_aliasing	1.630s	71.720us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.990s	158.586us	20	20	100.00
V2		TOTAL			686	700	98.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
		lc_ctrl_tl_intg_err	4.200s	224.249us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.200s	224.249us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.140s	1.412ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	32.240s	3.633ms	50	50	100.00
		lc_ctrl_sec_cm	38.570s	426.482us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.120s	641.903us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.550s	403.681us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.230s	4.006ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.600s	1.155ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.600s	1.155ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.720s	685.325us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.100s	4.204ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.100s	4.204ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.226h	569.755ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			992	1030	96.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.00	97.37	82.01	91.96	95.35	95.88	99.00	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:756) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 17 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 17 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.42497590894553228317367715628818580686807367425463923011147904398540554040071
      Line 37582, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 256403073681 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @ 256403073681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.44134518780925115554792286103803403400426215450064921363904587050128321177742
      Line 24508, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55407557698 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @ 55407557698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*) == * has 13 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 13 failures.

    • 0.lc_ctrl_volatile_unlock_smoke.102943818549468429393688118912396538315694113720519332016341357142062579281903
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10003031375 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x447ca904) == 0x1
        UVM_INFO @ 10003031375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_volatile_unlock_smoke.86693502302828572080570219842259185753623633317578654029671374073364054207899
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10001892752 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x597f5f04) == 0x1
        UVM_INFO @ 10001892752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (cip_base_vseq.sv:714) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 8.lc_ctrl_stress_all_with_rand_reset.81459236353972962927994107632852089006565187752244189364330395360883750823370
      Line 4633, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 838302340 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 838302340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.lc_ctrl_stress_all_with_rand_reset.14413387252771193664107862539360921805765758936237135550059246846549442038675
      Line 31277, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72633285242 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 72633285242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 33.lc_ctrl_stress_all.53831428858934416032694121925309259530420581809779110361638111594601133027198
      Line 3247, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 20283699912 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20283699912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.lc_ctrl_stress_all_with_rand_reset.23358283822103929955426269117839532521974375496046687675974453947871996395389
      Line 14572, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58374678279 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 58374678279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.56360258702197467940802135347600255098052234000880830792592426008777476286307
      Line 38472, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25497911791 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25497911791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 46.lc_ctrl_stress_all_with_rand_reset.92928012022589208744021139731917303980854401518349092308324016851957983665007
      Line 59728, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

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