LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.570s	457.189us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	44.718us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.200s	16.745us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.680s	239.268us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.760s	34.733us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	6.430s	337.061us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.200s	16.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.733us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.850s	792.520us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.600s	4.144ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.070s	11.343us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.540s	1.000ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.060s	2.770ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_prog_failure	5.540s	1.000ms	50	50	100.00
		lc_ctrl_errors	23.060s	2.770ms	50	50	100.00
		lc_ctrl_security_escalation	16.940s	3.199ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.585m	2.555ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.610s	6.262ms	20	20	100.00
		lc_ctrl_jtag_errors	1.750m	19.755ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.490s	1.959ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	39.530s	1.159ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.610s	6.262ms	20	20	100.00
		lc_ctrl_jtag_errors	1.750m	19.755ms	20	20	100.00
		lc_ctrl_jtag_access	25.830s	1.049ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.480s	3.604ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.650s	470.420us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.870s	148.585us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	16.300s	3.765ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	20.390s	1.901ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.800s	36.231us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.930s	1.303ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.070s	253.391us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	17.020s	2.934ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	7.195m	10.001ms	37	50	74.00
V2	stress_all	lc_ctrl_stress_all	15.285m	239.175ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.440s	64.444us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.720s	561.755us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.720s	561.755us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	44.718us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	16.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.733us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	56.729us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	44.718us	5	5	100.00
		lc_ctrl_csr_rw	1.200s	16.745us	20	20	100.00
		lc_ctrl_csr_aliasing	1.760s	34.733us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	56.729us	20	20	100.00
V2		TOTAL			685	700	97.86
V2S	tl_intg_err	lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.150s	1.556ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.150s	1.556ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.600s	4.144ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.480s	334.277us	50	50	100.00
		lc_ctrl_sec_cm	42.730s	1.244ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.940s	3.199ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.850s	792.520us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	39.530s	1.159ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.940s	1.379ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.940s	1.379ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	23.680s	1.668ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.930s	2.602ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.930s	2.602ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	29.344m	47.421ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*) == * has 13 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 13 failures.

    • 10.lc_ctrl_volatile_unlock_smoke.39460385587384941898011686935800333742487695000890769543833040295954057517228
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10001015319 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xc4766004) == 0x1
        UVM_INFO @ 10001015319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.lc_ctrl_volatile_unlock_smoke.109188509953777233553134596826646128878888885396778443724633996305824764019692
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10001577297 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0x44cc4704) == 0x1
        UVM_INFO @ 10001577297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (cip_base_vseq.sv:756) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 11 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 11 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.16438116831914174294650973696181821815896327198697447949451571449200914904375
      Line 1844, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2292440780 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @ 2292440780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.34743919093681354513117953469513230968240683022962380342814048016723384749249
      Line 367, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 103760292 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @ 103760292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 6.lc_ctrl_stress_all_with_rand_reset.56724067905589766130984840641627621250420258872676262399073653417820310601372
      Line 43219, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 100690989862 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 100690989862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.lc_ctrl_stress_all_with_rand_reset.84151937688584049247338591723439914923067842735767651507397779532452042989035
      Line 25425, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 138786768100 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 138786768100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 35.lc_ctrl_stress_all.87747106297510837778883412602613976756075933240091222477204812235098564084681
      Line 6646, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3643667178 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3643667178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:519) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.76994314177760111570517466713085132553997424249860159667650204332939752594707
      Line 45963, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36477354728 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 36477354728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.lc_ctrl_stress_all_with_rand_reset.49713119493806120695305802713135348728905225603868658171535040309057887324879
      Line 20285, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33689416407 ps: (cip_base_vseq.sv:519) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 33689416407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:714) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 34.lc_ctrl_stress_all_with_rand_reset.99317809756534100663400859297755668055615041769956038131741288729982907478122
      Line 9637, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19125219630 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 19125219630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.20342430065267803300128148266584875180365052986062780741688444013981991196999
      Line 5983, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12698079716 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 12698079716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 12.lc_ctrl_stress_all.42161809477016510177084961404253407195898810020167030664406968500092414192207
      Line 7295, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/12.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 26676673563 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 26676673563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 20.lc_ctrl_stress_all_with_rand_reset.98622509017063984361433487560247752242328883295270886300841709720778730116699
      Line 36170, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.28127680648875823667852623656175407226888920703773986719620141915686519617306
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:6310561d-f69b-4591-a59a-a2c67388a716
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:da3b3bc7-7caa-4672-a600-9b13abad68e1
      

Past Results

• Latest
• lint
• 2024.02.14_22.01.45
• 2024.02.08_09.10.36
• 2024.02.05_04.44.04
• 2024.01.31_20.53.30
• 2024.01.25_17.44.53
• 2024.01.22_10.59.35