LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.120s	134.619us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	69.272us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	20.088us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.720s	372.876us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.640s	168.337us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.940s	31.184us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	20.088us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	168.337us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.910s	172.742us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.940s	1.414ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.020s	13.595us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.140s	260.679us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.540s	1.046ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_prog_failure	5.140s	260.679us	50	50	100.00
		lc_ctrl_errors	23.540s	1.046ms	50	50	100.00
		lc_ctrl_security_escalation	19.230s	509.429us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.778m	15.952ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.190s	2.609ms	20	20	100.00
		lc_ctrl_jtag_errors	1.372m	3.154ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.870s	3.124ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.760s	6.154ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.190s	2.609ms	20	20	100.00
		lc_ctrl_jtag_errors	1.372m	3.154ms	20	20	100.00
		lc_ctrl_jtag_access	19.770s	1.672ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.110s	1.257ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.410s	129.008us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.670s	215.406us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.960s	1.746ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.730s	3.860ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.860s	158.419us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.140s	133.077us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.320s	860.246us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	26.150s	11.387ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.240s	68.550us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.716m	27.395ms	46	50	92.00
V2	alert_test	lc_ctrl_alert_test	1.400s	90.462us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.540s	647.391us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.540s	647.391us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	69.272us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	20.088us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	168.337us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.430s	39.468us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	69.272us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	20.088us	20	20	100.00
		lc_ctrl_csr_aliasing	1.640s	168.337us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.430s	39.468us	20	20	100.00
V2		TOTAL			696	700	99.43
V2S	tl_intg_err	lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.330s	703.134us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.330s	703.134us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.940s	1.414ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.360s	379.757us	50	50	100.00
		lc_ctrl_sec_cm	38.710s	3.006ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.230s	509.429us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.910s	172.742us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.760s	6.154ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.790s	668.395us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.790s	668.395us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.100s	1.062ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.920s	1.591ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.920s	1.591ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	39.713m	36.776ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			994	1030	96.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:774) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.62388775950050207428839113152055296629575388058029447262382404810163098127662
      Line 17179, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21859492646 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 21859492646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.53945497717762532229585088775808860675347091992090526342915049960662198821792
      Line 22488, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 188481137625 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 188481137625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all has 3 failures.

    • 6.lc_ctrl_stress_all.38041562587393464802951663784111515232513349331693241275561988422966117855055
      Line 8275, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 16327090030 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 16327090030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.lc_ctrl_stress_all.52401665258533285227900151107361858466602519955347502749763058629162175183038
      Line 11745, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3571990444 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 3571990444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.53252812051062977360806873747874923757449744257807786946263583624080046693285
      Line 77835, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44821564471 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 44821564471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:524) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.60794595124591604876757011055214644818971472554853599816127498003079218319252
      Line 17692, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20214405949 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 20214405949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.lc_ctrl_stress_all_with_rand_reset.70543501921472798450522244217984697821673115599946286420632612008553953347063
      Line 18241, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20854961192 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 20854961192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 31.lc_ctrl_stress_all_with_rand_reset.113920324097962150192149223010316347478193487330077624570236352417622197514715
      Line 44161, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 38.lc_ctrl_stress_all_with_rand_reset.43788382556371694577151085616297835474497882255856363139384099081714085805892
      Line 46614, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.102901023182203797617024003807492862198513179501862437229568080328869527922971
      Line 14386, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37180840069 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 37180840069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 36.lc_ctrl_stress_all.53874914301249548520889366852802616966702987432676317166558838140027867167301
      Line 4951, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2452138712 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2452138712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: Failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:7fee48cb-014d-48e0-8b62-bc0802a09933
      

Past Results

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