LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.210s	157.200us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	15.247us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.567us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	83.686us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.590s	87.310us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.030s	90.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.567us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	87.310us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.250s	107.809us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.210s	510.376us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.060s	12.823us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.140s	767.174us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	21.390s	1.913ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_prog_failure	6.140s	767.174us	50	50	100.00
		lc_ctrl_errors	21.390s	1.913ms	50	50	100.00
		lc_ctrl_security_escalation	20.520s	1.190ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.496m	8.913ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.270s	803.003us	20	20	100.00
		lc_ctrl_jtag_errors	2.207m	55.236ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.870s	3.801ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	1.923ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.270s	803.003us	20	20	100.00
		lc_ctrl_jtag_errors	2.207m	55.236ms	20	20	100.00
		lc_ctrl_jtag_access	25.940s	1.156ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	36.050s	1.268ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.860s	530.033us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.890s	229.279us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.460s	3.469ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	18.970s	6.498ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.470s	104.103us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.200s	473.387us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.480s	129.512us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	35.980s	3.010ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	9.035m	10.001ms	36	50	72.00
V2	stress_all	lc_ctrl_stress_all	7.887m	30.734ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	2.190s	427.503us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.370s	460.435us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.370s	460.435us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	15.247us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.567us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	87.310us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	95.243us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	15.247us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.567us	20	20	100.00
		lc_ctrl_csr_aliasing	1.590s	87.310us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	95.243us	20	20	100.00
V2		TOTAL			686	700	98.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
		lc_ctrl_tl_intg_err	6.710s	1.004ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.710s	1.004ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.210s	510.376us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	42.790s	926.780us	50	50	100.00
		lc_ctrl_sec_cm	42.440s	965.569us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	20.520s	1.190ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.250s	107.809us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	33.300s	1.923ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.020s	3.599ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.020s	3.599ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.560s	2.695ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	20.500s	720.771us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	20.500s	720.771us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	27.438m	49.106ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			985	1030	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.66	97.35	81.74	91.96	100.00	95.96	99.00	96.61

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:774) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.16536521761027840633265156229729609250800913458533751404716622492027865121225
      Line 7672, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 96450201104 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 96450201104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.62657306799160920711197097653559480796236785958467243014853658757365872641135
      Line 1635, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 733099553 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
        UVM_INFO @ 733099553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*) == * has 14 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 14 failures.

    • 10.lc_ctrl_volatile_unlock_smoke.76149387333530782748953189796569322894482458190438669927209488136996178287818
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10002036046 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xd5eb1904) == 0x1
        UVM_INFO @ 10002036046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.lc_ctrl_volatile_unlock_smoke.43069324320593366062274353698706536720988612623766676761684514143455131439681
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 10023391571 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xb1ae5904) == 0x1
        UVM_INFO @ 10023391571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (cip_base_vseq.sv:524) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.114813590822344568375601100870180740645249345222132704748518948455768784753364
      Line 12959, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43143358427 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 43143358427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.99048046499330378172678284982518593530628491170030841256686439145051577527716
      Line 8377, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7301575633 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7301575633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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