LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.140s	959.918us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.340s	20.853us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.140s	17.067us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.000s	47.007us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.750s	225.877us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.770s	45.122us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.140s	17.067us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	225.877us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.800s	204.699us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	29.140s	873.739us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	13.291us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.010s	299.070us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	19.430s	481.108us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_prog_failure	6.010s	299.070us	50	50	100.00
		lc_ctrl_errors	19.430s	481.108us	50	50	100.00
		lc_ctrl_security_escalation	19.130s	2.280ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.362m	5.241ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.450s	4.983ms	20	20	100.00
		lc_ctrl_jtag_errors	1.565m	13.318ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.290s	2.261ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	38.450s	1.223ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.450s	4.983ms	20	20	100.00
		lc_ctrl_jtag_errors	1.565m	13.318ms	20	20	100.00
		lc_ctrl_jtag_access	30.010s	1.319ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.010s	2.256ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.580s	585.102us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.230s	1.896ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.730s	1.620ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.000s	1.693ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.090s	320.081us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.380s	370.192us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.310s	180.269us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.130s	8.291ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	23.128us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.183m	82.212ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.260s	61.696us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.140s	262.237us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.140s	262.237us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.340s	20.853us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.067us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	225.877us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	183.096us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.340s	20.853us	5	5	100.00
		lc_ctrl_csr_rw	1.140s	17.067us	20	20	100.00
		lc_ctrl_csr_aliasing	1.750s	225.877us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	183.096us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.500s	460.576us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.500s	460.576us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	29.140s	873.739us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.500s	3.340ms	50	50	100.00
		lc_ctrl_sec_cm	38.830s	1.006ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.130s	2.280ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.800s	204.699us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	38.450s	1.223ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.790s	1.145ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.790s	1.145ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.170s	4.624ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.570s	462.654us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.570s	462.654us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.926h	134.088ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.82	96.40	95.74	95.35	98.10	99.00	96.07

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:788) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.40561619216315723739502856682766936813867744704128239249710939618252260110927
      Line 10476, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 46570813846 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 46570813846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.12388388167418340345826934301174018538376783627301841408728044917504327548286
      Line 27929, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21487540527 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21487540527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_vseq.sv:524) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.36941108796436894815245631584676848251995265994029646934753977949178355864219
      Line 14856, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 99464314295 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 99464314295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.lc_ctrl_stress_all_with_rand_reset.102341972336346774643914870195195741367389236414289500152154108510221119573754
      Line 46124, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 150839617998 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 150839617998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 29.lc_ctrl_stress_all_with_rand_reset.52052322874890648669356194707125872471723087013225730686429791591127400192586
      Line 4302, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7824139074 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7824139074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.73414585733372532070876862944712524551783689622884650022011071136767732817893
      Line 50110, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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