LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.360s	414.397us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.100s	35.142us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	16.661us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.130s	378.391us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.820s	33.164us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.640s	37.133us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	16.661us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	33.164us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.860s	91.264us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	27.020s	3.048ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	13.285us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	7.080s	947.455us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.640s	1.469ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_prog_failure	7.080s	947.455us	50	50	100.00
		lc_ctrl_errors	18.640s	1.469ms	50	50	100.00
		lc_ctrl_security_escalation	19.340s	7.327ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.102m	7.950ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	732.921us	20	20	100.00
		lc_ctrl_jtag_errors	2.165m	5.103ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.190s	7.844ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	30.910s	897.989us	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	732.921us	20	20	100.00
		lc_ctrl_jtag_errors	2.165m	5.103ms	20	20	100.00
		lc_ctrl_jtag_access	18.680s	777.819us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.620s	5.910ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.560s	189.219us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.940s	947.993us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.720s	2.139ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.710s	9.424ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.050s	198.646us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.820s	274.124us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.830s	93.469us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	22.780s	2.312ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.240s	13.967us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.256m	52.447ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.270s	97.388us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.390s	480.821us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.390s	480.821us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.100s	35.142us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.661us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	33.164us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	47.407us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.100s	35.142us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	16.661us	20	20	100.00
		lc_ctrl_csr_aliasing	1.820s	33.164us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.020s	47.407us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.960s	227.974us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.960s	227.974us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	27.020s	3.048ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.610s	456.168us	50	50	100.00
		lc_ctrl_sec_cm	41.880s	1.136ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.340s	7.327ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.860s	91.264us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	30.910s	897.989us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.550s	576.228us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.550s	576.228us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.200s	5.633ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.880s	1.044ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.880s	1.044ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.723h	153.607ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.79	95.71	95.73	97.62	98.34	98.76	96.79

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:815) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.106595120100772026139099460192621323852087557761876937028639282193711569927798
      Line 28140, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18982315149 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18982315149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.6908267413727709454811193125074679025137982204620228197092027607915094350989
      Line 7381, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8149343853 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8149343853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.82619154531948883058430119405198032964135779565077471821486464481810736783314
      Line 61184, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 10.lc_ctrl_stress_all_with_rand_reset.67659473213663969794881553573525165186233086477851300589427447364068907855973
      Line 40760, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_vseq.sv:542) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.lc_ctrl_stress_all_with_rand_reset.65668790215751745905633044025503492816414135711708740259090494238580427256680
      Line 48074, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21629328168 ps: (cip_base_vseq.sv:542) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 21629328168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.43926111109151215705717722922383434038893729992593457917757377724206261318329
      Line 18089, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42544158535 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 42544158535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.03.01_08.02.38
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• 2024.02.26_03.43.52
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