LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.850s	105.233us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	14.868us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	69.857us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	27.526us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.320s	152.235us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.020s	46.910us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	69.857us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	152.235us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.020s	228.449us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.550s	1.398ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	10.190us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.920s	292.940us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.720s	2.310ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_prog_failure	5.920s	292.940us	50	50	100.00
		lc_ctrl_errors	22.720s	2.310ms	50	50	100.00
		lc_ctrl_security_escalation	15.130s	1.723ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.409m	10.495ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.030s	386.196us	20	20	100.00
		lc_ctrl_jtag_errors	2.266m	5.363ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.400s	833.265us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	1.699ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	12.030s	386.196us	20	20	100.00
		lc_ctrl_jtag_errors	2.266m	5.363ms	20	20	100.00
		lc_ctrl_jtag_access	20.640s	6.687ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.910s	9.746ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.650s	534.550us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.830s	92.162us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	32.660s	1.482ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.420s	638.166us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.770s	172.973us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.250s	549.705us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.090s	664.761us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	52.050s	2.142ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	17.889us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	12.294m	72.676ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.330s	30.672us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.230s	161.486us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.230s	161.486us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	14.868us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	69.857us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	152.235us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	141.953us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	14.868us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	69.857us	20	20	100.00
		lc_ctrl_csr_aliasing	1.320s	152.235us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.850s	141.953us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
		lc_ctrl_tl_intg_err	4.320s	112.288us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.320s	112.288us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.550s	1.398ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	40.260s	697.983us	50	50	100.00
		lc_ctrl_sec_cm	37.950s	252.202us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.130s	1.723ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.020s	228.449us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.930s	1.699ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	32.450s	2.326ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	32.450s	2.326ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	22.830s	3.343ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.300s	1.047ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.300s	1.047ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.213h	29.821ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:815) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.54430517236732692258789678658687702534228960587301021684679646471002872662273
      Line 326, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 427600125 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 427600125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.32203099858831071160480509894103685231837569115357193652981018693584144942988
      Line 37105, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18355343270 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18355343270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:542) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.16781967978669565452442902035336435658504702035658310290560944665377584913771
      Line 33544, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43449252501 ps: (cip_base_vseq.sv:542) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 43449252501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.8244472795845006824072244497045023361131773235963111483576309776818287547054
      Line 25098, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 41483708777 ps: (cip_base_vseq.sv:542) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 41483708777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.114585435902030589154015671332292119113753043823221766856545282831345016787682
      Line 16355, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18017743494 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 18017743494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.21958495131576040374958221259063050313788296345882518412812888542956802150555
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:6518e1a3-a837-46c6-9033-b2661dd4fc53
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 29.lc_ctrl_stress_all.102522343259548104119391373654508036369943199656828427535019263756344976537513
      Line 4138, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 33531310930 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 33531310930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: Failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:1afc8f75-bcfe-45ed-86fa-a15d3c8eafa4
      

Past Results

• Latest
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• 2024.03.04_04.59.27
• 2024.03.01_08.02.38
• 2024.03.01_08.01.42
• 2024.02.26_03.43.52
• 2024.02.26_03.43.45
• 2024.02.22_05.00.36