LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.890s	390.602us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.400s	24.803us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	19.653us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.080s	63.822us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.790s	412.267us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.940s	108.477us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	19.653us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	412.267us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.070s	125.345us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.960s	400.959us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.040s	19.489us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.890s	486.626us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.660s	1.919ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_prog_failure	5.890s	486.626us	50	50	100.00
		lc_ctrl_errors	20.660s	1.919ms	50	50	100.00
		lc_ctrl_security_escalation	16.830s	1.425ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.994m	3.894ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.480s	2.773ms	20	20	100.00
		lc_ctrl_jtag_errors	1.843m	4.223ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.790s	2.741ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.020s	929.725us	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.480s	2.773ms	20	20	100.00
		lc_ctrl_jtag_errors	1.843m	4.223ms	20	20	100.00
		lc_ctrl_jtag_access	14.550s	3.727ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	39.600s	2.981ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.410s	226.838us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.640s	266.343us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.790s	12.496ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	15.810s	2.831ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.610s	22.958us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.520s	435.311us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.010s	64.957us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	32.890s	1.744ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.330s	16.080us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.355m	122.961ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.300s	95.266us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.630s	608.931us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.630s	608.931us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.400s	24.803us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	19.653us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	412.267us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.190s	93.901us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.400s	24.803us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	19.653us	20	20	100.00
		lc_ctrl_csr_aliasing	1.790s	412.267us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.190s	93.901us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
		lc_ctrl_tl_intg_err	4.700s	277.586us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.700s	277.586us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.960s	400.959us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.090s	1.466ms	50	50	100.00
		lc_ctrl_sec_cm	40.710s	524.774us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.830s	1.425ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.070s	125.345us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.020s	929.725us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	26.660s	3.657ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	26.660s	3.657ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.010s	1.805ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.050s	424.996us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.050s	424.996us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.648h	73.463ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.48	97.79	95.44	95.73	100.00	98.13	99.00	96.25

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 19 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.96318762854742845028261577618991379617517914648430343458178593740690151341118
      Line 7885, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5606184057 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5606184057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.lc_ctrl_stress_all_with_rand_reset.11334558011155574332423404215661875307404777404963067401425282340199612920236
      Line 5203, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7951356077 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7951356077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.33642075304797569982651872438374875883153961164011777513894731324619779665441
      Line 20401, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 83068704722 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 83068704722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.34282144879823916152006997028587037040971865623009922509635327439078919173639
      Line 21147, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16554310763 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 16554310763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 35.lc_ctrl_stress_all.42177014093466445199631015304523170950727428355014356503827049151562838553569
      Line 11691, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2975789277 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2975789277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.77765240743084254421091015284763060324036232500739946980880928435799326172062
      Line 57481, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 31.lc_ctrl_stress_all_with_rand_reset.9746740809993131787036189320514432651085450828319877034808876414345695601321
      Line 23678, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.7803101051348266138490261855872297108875690101022580325763091164917638822363
      Line 23238, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25868897738 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 25868897738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.lc_ctrl_stress_all_with_rand_reset.40841520348727987007071209255283242768098354710953545072613524708742749845526
      Line 11297, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16286340173 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 16286340173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 41.lc_ctrl_stress_all_with_rand_reset.113108075165513975181324657237374491466219729887958410214559403399493559941794
      Line 20984, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11751853181 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 11751853181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.04_05.00.38
• 2024.03.04_04.59.27
• 2024.03.01_08.02.38
• 2024.03.01_08.01.42
• 2024.02.26_03.43.52
• 2024.02.26_03.43.45