LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.940s	107.814us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	33.066us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.110s	65.770us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.520s	224.028us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.510s	150.753us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.030s	25.228us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.110s	65.770us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	150.753us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.870s	180.688us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.820s	331.235us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.080s	13.834us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.440s	347.885us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.710s	2.893ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_prog_failure	4.440s	347.885us	50	50	100.00
		lc_ctrl_errors	22.710s	2.893ms	50	50	100.00
		lc_ctrl_security_escalation	17.050s	454.245us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.270m	3.905ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.940s	2.964ms	20	20	100.00
		lc_ctrl_jtag_errors	1.314m	2.856ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.730s	845.194us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.950s	1.137ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.940s	2.964ms	20	20	100.00
		lc_ctrl_jtag_errors	1.314m	2.856ms	19	20	95.00
		lc_ctrl_jtag_access	29.790s	5.711ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.050s	2.607ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.250s	1.634ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.350s	125.279us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	28.860s	1.215ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.040s	1.758ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.540s	31.059us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.380s	418.053us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.320s	68.556us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.840s	791.611us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.310s	107.750us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	10.472m	38.609ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.350s	27.412us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.240s	195.353us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.240s	195.353us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	33.066us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	65.770us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	150.753us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	39.420us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	33.066us	5	5	100.00
		lc_ctrl_csr_rw	1.110s	65.770us	20	20	100.00
		lc_ctrl_csr_aliasing	1.510s	150.753us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.920s	39.420us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
		lc_ctrl_tl_intg_err	4.510s	440.811us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.510s	440.811us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.820s	331.235us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	41.500s	719.424us	50	50	100.00
		lc_ctrl_sec_cm	37.940s	782.527us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	17.050s	454.245us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.870s	180.688us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.950s	1.137ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.010s	628.180us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.010s	628.180us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.120s	13.015ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.900s	1.682ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.900s	1.682ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.109m	55.653ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1001	1030	97.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.97	97.82	96.21	93.31	97.62	98.52	99.00	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.80457762932772382156588903273234261001293226437395751713358012360536839379177
      Line 545, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1338437291 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1338437291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.77421951697505340922382017750091820563098986091973966488107990642310661000998
      Line 25008, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 89011330308 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 89011330308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 4 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.96156769107588739410848124513593750179835719910919700237944496813081660361340
      Line 30499, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 183943276078 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 183943276078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.lc_ctrl_stress_all_with_rand_reset.25268749923196391323714689903230607784950103934330213428998913917919211071029
      Line 43888, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 128387941782 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 128387941782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 21.lc_ctrl_stress_all.58902772226223799330413327153525678158696854480063156382282608807606591999884
      Line 8863, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7004093643 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 7004093643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.82940949916390002049582194044331645114619046362527511244972517589266822077562
      Line 43716, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55129191285 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 55129191285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.lc_ctrl_stress_all_with_rand_reset.71234215078548222529005441920897022810259805560313272542597348047090247087803
      Line 48736, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 78711610044 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 78711610044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 5.lc_ctrl_jtag_errors.32537587246826989140171706982597385237511410453597254230231582508774650065597
      Line 1707, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 2141064589 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2141064589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 16.lc_ctrl_volatile_unlock_smoke.63729246780492335156537090202736716785055454769060049680206514283407906349765
      Line 322, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 107749734 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.token_error (addr=0xdfd68404) == 0x1
        UVM_INFO @ 107749734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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