LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	15.690s	1.141ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.130s	25.165us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.130s	17.217us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.230s	115.082us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.650s	34.601us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.320s	189.983us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.130s	17.217us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.601us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.700s	1.793ms	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.650s	651.489us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.910s	38.659us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.480s	659.578us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.890s	561.754us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_prog_failure	6.480s	659.578us	50	50	100.00
		lc_ctrl_errors	23.890s	561.754us	50	50	100.00
		lc_ctrl_security_escalation	16.330s	509.059us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.632m	11.992ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.730s	904.333us	20	20	100.00
		lc_ctrl_jtag_errors	1.659m	17.733ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.610s	851.926us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.950s	1.716ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.730s	904.333us	20	20	100.00
		lc_ctrl_jtag_errors	1.659m	17.733ms	20	20	100.00
		lc_ctrl_jtag_access	18.450s	1.503ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.660s	1.175ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.090s	240.303us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.960s	153.663us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.290s	6.284ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.940s	2.018ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.450s	207.383us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.590s	200.386us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.840s	94.399us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.430s	1.495ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.310s	89.573us	49	50	98.00
V2	stress_all	lc_ctrl_stress_all	12.681m	78.253ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.530s	67.702us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.960s	595.680us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.960s	595.680us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.130s	25.165us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	17.217us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.601us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	185.221us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.130s	25.165us	5	5	100.00
		lc_ctrl_csr_rw	1.130s	17.217us	20	20	100.00
		lc_ctrl_csr_aliasing	1.650s	34.601us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.040s	185.221us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.590s	270.094us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.590s	270.094us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.650s	651.489us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.150s	404.770us	50	50	100.00
		lc_ctrl_sec_cm	37.560s	3.176ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.330s	509.059us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.700s	1.793ms	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.950s	1.716ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.160s	4.060ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.160s	4.060ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	33.710s	1.368ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.560s	2.161ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.560s	2.161ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.720h	35.905ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.15	97.89	95.50	93.31	100.00	98.55	98.51	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.15238975324626993577346468993258912461698805057993394307646584107556829665819
      Line 6932, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7630181149 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7630181149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.4480221801215384442463137343009704130830479991533248309620789140528254251376
      Line 23870, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7030338813 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7030338813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.lc_ctrl_stress_all_with_rand_reset.113630237975094209947645001068301946451126961241145218194127172622876416384744
      Line 19771, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11979392013 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 11979392013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all has 1 failures.

    • 45.lc_ctrl_stress_all.15716888757344069267191339842106395201545528963566953751716720477639309733654
      Line 9423, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 9800110395 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 9800110395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.40662559684118514575706140954413347055138175943973271013498142380341067955567
      Line 12716, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72408044082 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 72408044082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.lc_ctrl_stress_all_with_rand_reset.37052594316094217829442975647449457737520684362740217911332357674803646149109
      Line 21294, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 163435286627 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 163435286627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 10.lc_ctrl_stress_all_with_rand_reset.61548679166793961390195514210490171267440499136110581607581852622813560462283
      Line 8145, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8339804252 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8339804252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=*) == * has 1 failures:

  • Test lc_ctrl_volatile_unlock_smoke has 1 failures.

    • 48.lc_ctrl_volatile_unlock_smoke.92133549885219148473810766410542091381385567367639556307536934367047713276274
      Line 323, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest/run.log

        UVM_FATAL @ 129212847 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout lc_ctrl_reg_block.status.transition_successful (addr=0x81f7dc04) == 0x1
        UVM_INFO @ 129212847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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