Unified Coverage Report :: Module :: prim_lc_sender

Module : prim_lc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req	0.00	0.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en	0.00	0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00				0.00		u_lc_ctrl_signal_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	0.00	0.00				0.00

Line Coverage for Module : prim_lc_sender

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	66	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' or '../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
32	0	1
66	0	1