Unified Coverage Report :: Module :: lc_ctrl_signal_decode

Module : lc_ctrl_signal_decode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_flop_keymgr_div	0.00	0.00				0.00
u_prim_lc_sender_cpu_en	0.00	0.00				0.00
u_prim_lc_sender_creator_seed_sw_rw_en	0.00	0.00				0.00
u_prim_lc_sender_dft_en	0.00	0.00				0.00
u_prim_lc_sender_escalate_en	0.00	0.00				0.00
u_prim_lc_sender_hw_debug_en	0.00	0.00				0.00
u_prim_lc_sender_iso_part_sw_rd_en	0.00	0.00				0.00
u_prim_lc_sender_iso_part_sw_wr_en	0.00	0.00				0.00
u_prim_lc_sender_keymgr_en	0.00	0.00				0.00
u_prim_lc_sender_nvm_debug_en	0.00	0.00				0.00
u_prim_lc_sender_owner_seed_sw_rw_en	0.00	0.00				0.00
u_prim_lc_sender_raw_test_rma	0.00	0.00				0.00
u_prim_lc_sender_seed_hw_rd_en	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
TOTAL		63	0	0.00
ALWAYS	60	62	0	0.00
CONT_ASSIGN	296	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	0	1
61	0	1
62	0	1
63	0	1
64	0	1
65	0	1
66	0	1
67	0	1
68	0	1
69	0	1
70	0	1
72	0	1
74	0	1
76	0	1
79	0	1
92	0	1
93	0	1
104	0	1
116	0	1
117	0	1
118	0	1
119	0	1
120	0	1
121	0	1
122	0	1
129	0	1
130	0	1
131	0	1
132	0	1
133	0	1
134	0	1
140	0	1
141	0	1
142	0	1
143	0	1
144	0	1
145	0	1
149	0	1
152	0	1
159	0	1
160	0	1
161	0	1
162	0	1
163	0	1
164	0	1
168	0	1
171	0	1
176	0	1
177	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
197	0	1
204	0	1
211	0	1
296	0	1

---

Branch Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
Branches		12	0	0.00
CASE	76	12	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	case (fsm_state_i)
-2-:	92	if (lc_state_valid_i)
-3-:	93	case (lc_state_i)

Branches:

-1-	-2-	-3-	Status	Tests
ResetSt	-	-	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-1: LcStRaw LcStTestLocked0 LcStTestLocked1 LcStTestLocked2 LcStTestLocked3 LcStTestLocked4 LcStTestLocked5 LcStTestLocked6	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-2: LcStTestUnlocked0 LcStTestUnlocked1 LcStTestUnlocked2 LcStTestUnlocked3 LcStTestUnlocked4 LcStTestUnlocked5 LcStTestUnlocked6	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStTestUnlocked7	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStProd LcStProdEnd	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStDev	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStRma	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	default	Not Covered
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	0	-	Not Covered
PostTransSt	-	-	Not Covered
ScrapSt EscalateSt InvalidSt	-	-	Not Covered
default	-	-	Not Covered