Unified Coverage Report :: Module :: tlul_rsp_intg_chk

Module : tlul_rsp_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk	0.00	0.00	0.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
5.03	0.00	0.00	15.09

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	15.09			15.09

Line Coverage for Module : tlul_rsp_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
CONT_ASSIGN	23	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	50	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	0	1
47	0	1
50	0	1

---

Cond Coverage for Module : tlul_rsp_intg_chk

	Total	Covered	Percent
Conditions	5	0	0.00
Logical	5	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
CONT_ASSIGN	23	1	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	50	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	0	1
47	0	1
50	0	1

---

Cond Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Excluded		VC_COV_UNR

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Unreachable
1	0	Excluded		VC_COV_UNR