Unified Coverage Report :: Module :: tlul_adapter_host

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_tap_tlul_host

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
3.77	0.00	0.00	15.09		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	0.00	0.00
u_rsp_chk	5.03	0.00	0.00	15.09

Line Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
TOTAL		23	0	0.00
ALWAYS	70	3	0	0.00
ALWAYS	78	5	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	119	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	132	4	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	0	1
71	0	1
73	0	1
78	0	1
80	0	1
81	0	1
82	0	1
84	0	1
			==> MISSING_ELSE
89	0	1
94	0	1
96	0	1
116	0	1
118	0	1
119	0	1
120	0	1
132	0	1
133	0	1
134	0	1
135	0	1
			==> MISSING_ELSE
141	0	1
145	0	1
149	0	1
153	0	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Module : tlul_adapter_host

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
TERNARY	94	2	0	0.00
IF	132	3	0	0.00
IF	70	2	0	0.00
IF	80	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

Line Coverage for Instance : tb.dut.u_tap_tlul_host

	Line No.	Total	Covered	Percent
TOTAL		22	0	0.00
ALWAYS	70	3	0	0.00
ALWAYS	78	5	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	118	1	0	0.00
CONT_ASSIGN	119	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	132	3	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	0	1
71	0	1
73	0	1
78	0	1
80	0	1
81	0	1
82	0	1
84	0	1
			==> MISSING_ELSE
89	0	1
94	0	1
96	0	1
116	0	1
118	0	1
119	0	1
120	0	1
132	0	1
133	0	1
134	0	1
135		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
141	0	1
145	0	1
149	0	1
153	0	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Instance : tb.dut.u_tap_tlul_host

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		VC_COV_UNR
1	0	Not Covered

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

---

Branch Coverage for Instance : tb.dut.u_tap_tlul_host

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	94	2	0	0.00
IF	132	2	0	0.00
IF	70	2	0	0.00
IF	80	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Not Covered
0	1	Excluded		VC_COV_UNR
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered