Unified Coverage Report :: Module :: tlul_cmd_intg_gen

Module : tlul_cmd_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_cmd_intg_gen	0.00	0.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_cmd_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_data_gen	0.00	0.00
u_cmd_gen	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	46	4	0	0.00
CONT_ASSIGN	54	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	0	1
33	0	1
46	0	1
47	0	1
48	0	1
49	0	1
54	0	1