Unified Coverage Report :: Module :: prim_clock_mux2

Module : prim_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_clock_mux2_0/prim_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux	0.00			0.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux	0.00			0.00
tb.dut.u_prim_clock_mux2
tb.dut.u_prim_rst_n_mux2

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00			0.00				gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00			0.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00			0.00				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00			0.00

---

Module Instance : tb.dut.u_prim_clock_mux2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00	0.00	0.00

---

Module Instance : tb.dut.u_prim_rst_n_mux2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00	0.00	0.00

Toggle Coverage for Module : prim_clock_mux2

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	8	0	0.00
Total Bits 0->1	4	0	0.00
Total Bits 1->0	4	0	0.00

Ports	4	0	0.00
Port Bits	8	0	0.00
Port Bits 0->1	4	0	0.00
Port Bits 1->0	4	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	No	No		No		INPUT
clk1_i	No	No		No		INPUT
sel_i	No	No		No		INPUT
clk_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux