Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| testmode_i |
No |
No |
|
No |
|
INPUT |
| test_rst_ni |
No |
No |
|
No |
|
INPUT |
| tck_i |
No |
No |
|
No |
|
INPUT |
| trst_ni |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_req_i.data[31:0] |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_req_i.op[1:0] |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_req_i.addr[31:0] |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_ready_o |
No |
No |
|
No |
|
OUTPUT |
| jtag_dmi_valid_i |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_cdc_clear_i |
No |
No |
|
No |
|
INPUT |
| jtag_dmi_resp_o.resp[1:0] |
No |
No |
|
No |
|
OUTPUT |
| jtag_dmi_resp_o.data[31:0] |
No |
No |
|
No |
|
OUTPUT |
| jtag_dmi_valid_o |
No |
No |
|
No |
|
OUTPUT |
| jtag_dmi_ready_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| clk_i |
No |
No |
|
No |
|
INPUT |
| rst_ni |
No |
No |
|
No |
|
INPUT |
| core_dmi_rst_no |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_req_o.data[31:0] |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_req_o.op[1:0] |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_req_o.addr[31:0] |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_valid_o |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_ready_i |
No |
No |
|
No |
|
INPUT |
| core_dmi_resp_i.resp[1:0] |
No |
No |
|
No |
|
INPUT |
| core_dmi_resp_i.data[31:0] |
No |
No |
|
No |
|
INPUT |
| core_dmi_ready_o |
No |
No |
|
No |
|
OUTPUT |
| core_dmi_valid_i |
No |
No |
|
No |
|
INPUT |