Unified Coverage Report :: Module :: prim_fifo_async_simple

Module : prim_fifo_async_simple

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req	0.00			0.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp	0.00			0.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00			0.00				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	0.00			0.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00			0.00				i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	0.00			0.00

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=66,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

	Total	Covered	Percent
Totals	10	0	0.00
Total Bits	280	0	0.00
Total Bits 0->1	140	0	0.00
Total Bits 1->0	140	0	0.00

Ports	10	0	0.00
Port Bits	280	0	0.00
Port Bits 0->1	140	0	0.00
Port Bits 1->0	140	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_wr_i	No	No		No		INPUT
rst_wr_ni	No	No		No		INPUT
wvalid_i	No	No		No		INPUT
wready_o	No	No		No		OUTPUT
wdata_i[65:0]	No	No		No		INPUT
clk_rd_i	No	No		No		INPUT
rst_rd_ni	No	No		No		INPUT
rvalid_o	No	No		No		OUTPUT
rready_i	No	No		No		INPUT
rdata_o[65:0]	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_fifo_async_simple ( parameter Width=34,EnRstChks=0,EnRzHs=1 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
0.00	0.00

tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp

	Total	Covered	Percent
Totals	9	0	0.00
Total Bits	150	0	0.00
Total Bits 0->1	75	0	0.00
Total Bits 1->0	75	0	0.00

Ports	9	0	0.00
Port Bits	150	0	0.00
Port Bits 0->1	75	0	0.00
Port Bits 1->0	75	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_wr_i	No	No		No		INPUT
rst_wr_ni	No	No		No		INPUT
wvalid_i	No	No		No		INPUT
wready_o	No	No		No		OUTPUT
wdata_i[33:0]	No	No		No		INPUT
clk_rd_i	No	No		No		INPUT
rst_rd_ni	No	No		No		INPUT
rvalid_o	No	No		No		OUTPUT
rready_i	Unreachable	Unreachable		Unreachable		INPUT
rdata_o[33:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp