OTBN Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	87.899us	1	1	100.00
V1	single_binary	otbn_single	47.000s	190.694us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	18.987us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	23.904us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	640.949us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	23.648us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	29.759us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	23.904us	20	20	100.00
		otbn_csr_aliasing	7.000s	23.648us	5	5	100.00
V1	mem_walk	otbn_mem_walk	37.000s	1.203ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	291.493us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	46.000s	853.787us	10	10	100.00
V2	multi_error	otbn_multi_err	47.000s	850.456us	1	1	100.00
V2	back_to_back	otbn_multi	1.000m	534.101us	10	10	100.00
V2	stress_all	otbn_stress_all	3.083m	914.831us	10	10	100.00
V2	lc_escalation	otbn_escalate	25.000s	82.261us	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	29.080us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	67.680us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	18.490us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	16.078us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	117.346us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	117.346us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	18.987us	5	5	100.00
		otbn_csr_rw	6.000s	23.904us	20	20	100.00
		otbn_csr_aliasing	7.000s	23.648us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	55.457us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	18.987us	5	5	100.00
		otbn_csr_rw	6.000s	23.904us	20	20	100.00
		otbn_csr_aliasing	7.000s	23.648us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	55.457us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	13.000s	37.921us	10	10	100.00
		otbn_dmem_err	12.000s	103.132us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	90.402us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.233m	251.299us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	57.095us	5	5	100.00
		otbn_urnd_err	11.000s	62.208us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	22.686us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	64.197us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
		otbn_tl_intg_err	31.000s	325.993us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	233.880us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	87.899us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	103.132us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	37.921us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	325.993us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	82.261us	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	37.921us	10	10	100.00
		otbn_dmem_err	12.000s	103.132us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	29.080us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.686us	5	5	100.00
		otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	37.921us	10	10	100.00
		otbn_dmem_err	12.000s	103.132us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	29.080us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.686us	5	5	100.00
		otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	82.261us	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	37.921us	10	10	100.00
		otbn_dmem_err	12.000s	103.132us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	29.080us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	22.686us	5	5	100.00
		otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	65.396us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	60.624us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	36.000s	144.008us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	36.000s	144.008us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	29.326us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	115.557us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	2.433m	10.004ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	2.433m	10.004ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	240.856us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.000m	534.101us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	23.000s	103.478us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	47.000s	190.694us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.150m	1.871ms	5	5	100.00
V2S		TOTAL			150	153	98.04
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	19.767m	4.487ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			566	575	98.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	19	19	16	84.21
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	99.52	94.24	99.63	93.64	93.61	97.44	91.28	99.16

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

12.otbn_escalate.115154062262021104011650582670272799324869377937473952649102151174438492244261
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log

  UVM_FATAL @   7357551 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   7357551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.otbn_escalate.12921110474099125513585433339834626702943333623255204113922974412279356070269
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log

  UVM_FATAL @   9821462 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   9821462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:

Test otbn_escalate has 2 failures.

39.otbn_escalate.37729590116758085569891033168462953562747880278164905421698148588056654650090
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log

  UVM_FATAL @  54930899 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  54930899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.otbn_escalate.81564232150800963977620046227862560518596186723067438322076480252766869258465
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/40.otbn_escalate/latest/run.log

  UVM_FATAL @  20028287 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  20028287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 0.otbn_stack_addr_integ_chk.42299462573508795544519474922271527830592815350202410200977802558186877293526
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10004426281 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10004426281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

Test otbn_ctrl_redun has 1 failures.

3.otbn_ctrl_redun.2079972559672835327869554329617926406933857752246375103812580724365836096565
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8871639 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8871639 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   8871639 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8871639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.46187653599059919320990455383138784117690404034590109107848164847706979821874
    Line 345, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 382764294 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 382764294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:31) virtual_sequencer [otbn_rf_base_intg_err_vseq] Register file was not used before time limit has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 8.otbn_rf_base_intg_err.58064780614253139873307232552439701045159117477806176820509703377349397127112
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @ 209391551 ps: (otbn_rf_base_intg_err_vseq.sv:31) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Register file was not used before time limit
  UVM_INFO @ 209391551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_escalate has 1 failures.
  - 41.otbn_escalate.15262542543271013432612106464377217059604811703707691713525805490700642197715
    Line 301, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_escalate/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 15433211 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  15433211 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @  15433211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```