OTP_CTRL Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.750s 252.384us 1 1 100.00
V1 smoke otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 2.500s 1.391ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.120s 587.624us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 9.950s 2.032ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 4.050s 133.953us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 5.830s 1.611ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.120s 587.624us 20 20 100.00
otp_ctrl_csr_aliasing 4.050s 133.953us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.410s 54.265us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.420s 519.958us 5 5 100.00
V1 TOTAL 116 116 100.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 18.720s 738.839us 1 1 100.00
V2 init_fail otp_ctrl_init_fail 9.030s 2.535ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 21.560s 12.404ms 10 10 100.00
otp_ctrl_check_fail 22.530s 2.795ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 10.660s 3.628ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 1.750m 5.826ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 22.210s 2.896ms 50 50 100.00
otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 21.290s 9.618ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 43.540s 21.085ms 50 50 100.00
V2 test_access otp_ctrl_test_access 36.350s 11.251ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 5.293m 44.118ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 1.870s 558.259us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 6.650s 857.829us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 7.460s 2.441ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 7.460s 2.441ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 2.500s 1.391ms 5 5 100.00
otp_ctrl_csr_rw 2.120s 587.624us 20 20 100.00
otp_ctrl_csr_aliasing 4.050s 133.953us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.360s 1.723ms 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 2.500s 1.391ms 5 5 100.00
otp_ctrl_csr_rw 2.120s 587.624us 20 20 100.00
otp_ctrl_csr_aliasing 4.050s 133.953us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.360s 1.723ms 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
otp_ctrl_tl_intg_err 44.280s 18.872ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 44.280s 18.872ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_macro_errs 43.540s 21.085ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_macro_errs 43.540s 21.085ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 12.190s 7.074ms 200 200 100.00
otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 9.030s 2.535ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 22.530s 2.795ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 2.209m 17.275ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 2.686m 8.654ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 10.660s 3.628ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 24.700s 3.331ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 43.540s 21.085ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 18.560s 7.565ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 2.851h 3.884s 96 100 96.00
V3 TOTAL 97 101 96.04
TOTAL 1339 1343 99.70

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.51 92.65 91.61 92.31 92.68 93.51 96.53 95.27

Failure Buckets

Past Results