OTP_CTRL Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.960s	236.901us	1	1	100.00
V1	smoke	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.290s	90.470us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.290s	589.600us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.830s	1.583ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.400s	428.071us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.990s	195.674us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.290s	589.600us	20	20	100.00
		otp_ctrl_csr_aliasing	4.400s	428.071us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.490s	539.420us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.400s	99.303us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.140s	324.348us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.590s	2.125ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	20.630s	1.306ms	10	10	100.00
		otp_ctrl_check_fail	32.670s	8.628ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.970s	5.171ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	27.200s	10.174ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	24.740s	3.220ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	21.610s	6.472ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	41.970s	5.090ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	28.340s	10.801ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	4.325m	54.492ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.200s	581.688us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.000s	989.871us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.900s	2.899ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.900s	2.899ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.290s	90.470us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	589.600us	20	20	100.00
		otp_ctrl_csr_aliasing	4.400s	428.071us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.740s	1.362ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.290s	90.470us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	589.600us	20	20	100.00
		otp_ctrl_csr_aliasing	4.400s	428.071us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.740s	1.362ms	20	20	100.00
V2		TOTAL			1099	1101	99.82
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.640s	9.772ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.640s	9.772ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_macro_errs	41.970s	5.090ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_macro_errs	41.970s	5.090ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	16.250s	6.728ms	200	200	100.00
		otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.590s	2.125ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	32.670s	8.628ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	31.940s	10.433ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.703m	17.675ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.970s	5.171ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	29.020s	3.048ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	41.970s	5.090ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.790s	3.032ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.755h	3.547s	94	100	94.00
V3		TOTAL			95	101	94.06
		TOTAL			1335	1343	99.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.38	92.61	91.06	92.23	92.68	93.33	96.53	95.19

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.69016624335148864147176298522610030913474534482560955201243715602006227681045
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c651906b-2bf7-475f-a139-5b65c46bf89e
```
  - 43.otp_ctrl_stress_all_with_rand_reset.110702805365514265382163483326523877033296820782507370885048321160302030905577
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a140057c-ee6c-450f-bac3-35bc125a3e32
```
  - ... and 3 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1311267) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

1.otp_ctrl_stress_all.21864119846801088359961908054522033028767629055396474549503559173344584934032
Line 308, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8631184337 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1311267) { a_addr: 'ha753afe8  a_data: 'hdfe48acd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h60  a_opcode: 'h0  a_user: 'h2752b  d_param: 'h0  d_source: 'h60  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 8631184337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@34134) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

11.otp_ctrl_test_access.92095888779815538217552873004799667885061976933162221045662819164300102559414
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 517661565 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@34134) { a_addr: 'h3c4b6a14  a_data: 'h5dd6bfa3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha6  a_opcode: 'h0  a_user: 'h24d7b  d_param: 'h0  d_source: 'ha6  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 517661565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.otp_ctrl_stress_all_with_rand_reset.72780832779195990739910226581839714957100190799534742242392617322976200859678
    Line 271, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 190046861 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 190046861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```