8faf04697a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 3.050s | 807.107us | 1 | 1 | 100.00 |
| V1 | smoke | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 4.050s | 1.419ms | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 2.450s | 546.239us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 11.760s | 1.567ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 6.640s | 1.224ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 8.480s | 222.767us | 10 | 20 | 50.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.450s | 546.239us | 20 | 20 | 100.00 |
| otp_ctrl_csr_aliasing | 6.640s | 1.224ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 1.390s | 39.323us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.670s | 506.064us | 5 | 5 | 100.00 |
| V1 | TOTAL | 106 | 116 | 91.38 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 20.280s | 607.427us | 1 | 1 | 100.00 |
| V2 | init_fail | otp_ctrl_init_fail | 8.200s | 2.348ms | 300 | 300 | 100.00 |
| V2 | partition_check | otp_ctrl_background_chks | 26.370s | 2.805ms | 10 | 10 | 100.00 |
| otp_ctrl_check_fail | 1.401m | 15.419ms | 45 | 50 | 90.00 | ||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 12.660s | 4.054ms | 50 | 50 | 100.00 |
| V2 | partition_lock | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 43.060s | 19.162ms | 50 | 50 | 100.00 |
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 32.130s | 10.454ms | 50 | 50 | 100.00 |
| otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 | ||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 48.870s | 15.667ms | 50 | 50 | 100.00 |
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 57.650s | 21.861ms | 50 | 50 | 100.00 |
| V2 | test_access | otp_ctrl_test_access | 2.168m | 30.715ms | 46 | 50 | 92.00 |
| V2 | stress_all | otp_ctrl_stress_all | 7.076m | 119.308ms | 50 | 50 | 100.00 |
| V2 | intr_test | otp_ctrl_intr_test | 2.130s | 575.973us | 50 | 50 | 100.00 |
| V2 | alert_test | otp_ctrl_alert_test | 3.790s | 331.070us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 8.080s | 680.370us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 8.080s | 680.370us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 4.050s | 1.419ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.450s | 546.239us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.640s | 1.224ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 4.480s | 1.880ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 4.050s | 1.419ms | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.450s | 546.239us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.640s | 1.224ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 4.480s | 1.880ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1092 | 1101 | 99.18 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| otp_ctrl_tl_intg_err | 31.420s | 18.992ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 31.420s | 18.992ms | 20 | 20 | 100.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_macro_errs | 57.650s | 21.861ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_macro_errs | 57.650s | 21.861ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 38.180s | 5.175ms | 200 | 200 | 100.00 |
| otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 8.200s | 2.348ms | 300 | 300 | 100.00 |
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 1.401m | 15.419ms | 45 | 50 | 90.00 |
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 48.290s | 20.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 5.195m | 170.017ms | 5 | 5 | 100.00 |
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 12.660s | 4.054ms | 50 | 50 | 100.00 |
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 17.360s | 6.698ms | 50 | 50 | 100.00 |
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 57.650s | 21.861ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 11.580s | 5.895ms | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 2.895h | 9.401s | 50 | 100 | 50.00 |
| V3 | TOTAL | 51 | 101 | 50.50 | |||
| TOTAL | 1274 | 1343 | 94.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 17 | 17 | 15 | 88.24 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.16 | 91.52 | 89.81 | 89.53 | 72.35 | 91.55 | 96.33 | 93.07 |
UVM_ERROR (cip_base_vseq.sv:756) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 35 failures:
1.otp_ctrl_stress_all_with_rand_reset.29121721304396783821443788604213484525606484597443050076184374182052949621236
Line 67048, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 748472090783 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 748472090783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otp_ctrl_stress_all_with_rand_reset.32387962784632835567165168059224346583832298407873952285328708964530013505043
Line 8187, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 135809657 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 135809657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_ERROR (cip_base_vseq.sv:714) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 19 failures:
0.otp_ctrl_stress_all_with_rand_reset.68668307933505914291843646402447199676697984706959337147370679202016429922
Line 55832, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 478974058362 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 478974058362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otp_ctrl_stress_all_with_rand_reset.70326588659981090809362839485385082810991384409478126331942489824900606092755
Line 1061, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 116720997047 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 116720997047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
4.otp_ctrl_csr_mem_rw_with_rand_reset.12183261057970960398734913147833522858501341007370199862107639168427823849696
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 105417009 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 105417009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.otp_ctrl_csr_mem_rw_with_rand_reset.11289294819640639913728237808345357728175828584481492534193980562321633370646
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 37033220 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 37033220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 5 failures:
17.otp_ctrl_check_fail.108203983922563718644830118654286110349594295714098963012508412928866532545392
Line 4655, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest/run.log
UVM_ERROR @ 159688323 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
UVM_INFO @ 159688323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.otp_ctrl_check_fail.57544433073164278797108205156141366002592059246547979444325792959618640111368
Line 18078, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest/run.log
UVM_ERROR @ 505806121 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
UVM_INFO @ 505806121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
16.otp_ctrl_stress_all_with_rand_reset.115039972717441206896829417122548796232161042565979185352965947583002360729459
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2341c6e9-8d66-4b67-a147-b155553feca7
58.otp_ctrl_stress_all_with_rand_reset.78444125417642267843922401327225436007884766954352295751532666494406664763456
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4ca6882a-2fe2-43e3-ad5b-cd8216b0b7ac
... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@146773) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.otp_ctrl_test_access.76312861806961892446923804768579862168971942648130137950880575440641868094793
Line 8861, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest/run.log
UVM_ERROR @ 205625075 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@146773) { a_addr: 'h68a7e3b0 a_data: 'h5d12e1e2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he4 a_opcode: 'h1 a_user: 'h2736a d_param: 'h0 d_source: 'he4 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 205625075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@234541) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
23.otp_ctrl_test_access.41237758720316743442941726711730862822457004564032806815487648782605251641724
Line 13690, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest/run.log
UVM_ERROR @ 3259362604 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@234541) { a_addr: 'h4bd0b90c a_data: 'h685d7fc4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc1 a_opcode: 'h1 a_user: 'h24068 d_param: 'h0 d_source: 'hc1 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 3259362604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@261411) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.otp_ctrl_test_access.86578345532037778484292128834398710312943984986906993699866314091058028370085
Line 16016, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest/run.log
UVM_ERROR @ 1641521615 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@261411) { a_addr: 'h94f6a320 a_data: 'h4f2a77dc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h1 a_user: 'h24f74 d_param: 'h0 d_source: 'h2e d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 1641521615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@165959) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
42.otp_ctrl_test_access.109600562991881133908022657344911156646301653733731081647196638904900839310789
Line 9707, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest/run.log
UVM_ERROR @ 5913635356 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@165959) { a_addr: 'h90e4ee3c a_data: 'h92777c4b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h0 a_user: 'h26334 d_param: 'h0 d_source: 'h3b d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 5913635356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28183477) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
43.otp_ctrl_stress_all_with_rand_reset.10500888039939896794086698204002706835700794156390798875812287514962546133411
Line 28061, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1672827560569 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28183477) { a_addr: 'h6f2d606c a_data: 'ha7cb928f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd9 a_opcode: 'h0 a_user: 'h27204 d_param: 'h0 d_source: 'hd9 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 1672827560569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:
64.otp_ctrl_stress_all_with_rand_reset.25908466471210694505213323848400203179634538833827524521556147654939672210987
Line 42494, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 21080047563 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
UVM_INFO @ 21080467563 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 21080487563 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 21081067563 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 21081107563 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@253609) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
66.otp_ctrl_stress_all_with_rand_reset.14244228380898900022085708192738921769653932062048744617863489448946992633054
Line 8325, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1121256751 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@253609) { a_addr: 'hf9e8fdc8 a_data: 'hba5d978 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h92 a_opcode: 'h1 a_user: 'h26715 d_param: 'h0 d_source: 'h92 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, access gated by lc_dft_en_i
UVM_INFO @ 1121256751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---