OTP_CTRL Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.840s	66.929us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.550s	198.849us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.840s	159.806us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.150s	1.906ms	4	5	80.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.030s	2.014ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.180s	1.604ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.840s	159.806us	20	20	100.00
		otp_ctrl_csr_aliasing	5.030s	2.014ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.460s	45.656us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.630s	512.336us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	29.680s	9.907ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.390s	2.584ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	6.510s	340.425us	0	10	0.00
		otp_ctrl_check_fail	14.450s	1.878ms	1	50	2.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.980s	4.274ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2	interface_key_check	otp_ctrl_parallel_key_req	7.480s	2.464ms	0	50	0.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	13.200s	6.564ms	1	50	2.00
		otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2	otp_dai_errors	otp_ctrl_dai_errs	9.710s	1.813ms	0	50	0.00
V2	otp_macro_errors	otp_ctrl_macro_errs	29.660s	4.087ms	1	50	2.00
V2	test_access	otp_ctrl_test_access	7.390s	584.629us	1	50	2.00
V2	stress_all	otp_ctrl_stress_all	19.270s	3.437ms	0	50	0.00
V2	intr_test	otp_ctrl_intr_test	1.980s	561.488us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.010s	840.648us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.470s	2.320ms	19	20	95.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.470s	2.320ms	19	20	95.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.550s	198.849us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	159.806us	20	20	100.00
		otp_ctrl_csr_aliasing	5.030s	2.014ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.230s	2.025ms	19	20	95.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.550s	198.849us	5	5	100.00
		otp_ctrl_csr_rw	1.840s	159.806us	20	20	100.00
		otp_ctrl_csr_aliasing	5.030s	2.014ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.230s	2.025ms	19	20	95.00
V2		TOTAL			582	1101	52.86
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
		otp_ctrl_tl_intg_err	35.230s	19.464ms	19	20	95.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	35.230s	19.464ms	19	20	95.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_macro_errs	29.660s	4.087ms	1	50	2.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_macro_errs	29.660s	4.087ms	1	50	2.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	19.750s	1.472ms	89	200	44.50
		otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.390s	2.584ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	14.450s	1.878ms	1	50	2.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	5.720s	666.113us	0	50	0.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.849m	131.374ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.980s	4.274ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.390s	6.460ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	29.660s	4.087ms	1	50	2.00
V2S		TOTAL			24	25	96.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	20.890s	7.864ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.473h	445.203ms	1	100	1.00
V3		TOTAL			2	101	1.98
		TOTAL			722	1343	53.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	7	77.78
V2	17	17	5	29.41
V2S	2	2	1	50.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.47	91.60	89.36	85.02	79.05	91.53	95.59	73.13

Failure Buckets

Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 613 failures:

Test otp_ctrl_background_chks has 10 failures.

0.otp_ctrl_background_chks.67036122210101031795180678725035631519323714980764301323302986394176264608707
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 346183124 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

1.otp_ctrl_background_chks.86001016695695946000583877891462245762381999652330363451404282930933499519452
Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 109734172 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

... and 8 more failures.

Test otp_ctrl_parallel_lc_req has 49 failures.

0.otp_ctrl_parallel_lc_req.69762957881582811881668604275733403315899103877214524205969870157033436674463
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 95302620 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

1.otp_ctrl_parallel_lc_req.73729379655083561626086384790853432102137618365926308520129812921995274543897
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1523216911 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

... and 47 more failures.

Test otp_ctrl_dai_lock has 50 failures.

0.otp_ctrl_dai_lock.16341618404030596756698827033596554325679513076973518257687505168144471204156
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 236995653 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

1.otp_ctrl_dai_lock.112395327363664131496178337027701540149503896629332771194137450980204586225481
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 487822363 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

... and 48 more failures.

Test otp_ctrl_dai_errs has 50 failures.

0.otp_ctrl_dai_errs.10349571318573411159733820137865802241559190437624592715536485848261520293412
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 17
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1812936469 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

1.otp_ctrl_dai_errs.85260540680272338883317281564881389413564536873672385800411474473735642225360
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 46714949 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

... and 48 more failures.

Test otp_ctrl_check_fail has 48 failures.

0.otp_ctrl_check_fail.53457458887018803179834091463272341670465148882982877238083788392332659385169
Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 224
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 208806015 ps, Illegal bin
    vendor_test_ecc_uncorrectable_err of cross dai_err_code_for_all_partitions

1.otp_ctrl_check_fail.41684710211540430093733790542676124029168050875158466420245524824560821538594
Line 266, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 223216040 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

... and 46 more failures.

... and 6 more tests.

Job otp_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test otp_ctrl_csr_bit_bash has 1 failures.
  - 1.otp_ctrl_csr_bit_bash.14356225242964922190708492581156677589121741130048387753789208654104428732588
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest/run.log
```
  Job ID: smart:62275069-0617-4548-adc4-5624bfb00ea7
```
- Test otp_ctrl_tl_errors has 1 failures.
  - 13.otp_ctrl_tl_errors.76026785253905071083691027425364376280317400790556781092148820882395762933641
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest/run.log
```
  Job ID: smart:e425176f-c95b-4616-874e-431efd77d794
```

Error-[FCIBH] Illegal bin hit has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

14.otp_ctrl_stress_all_with_rand_reset.22386519638233518058324018014666401653297815510435356733800667990813264634829
Line 289, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 17
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4935779227 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

77.otp_ctrl_stress_all_with_rand_reset.66023451784305108708129054332068046796167846182651956448509490521303735605130
Line 541, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv, 40
  otp_ctrl_env_pkg, "otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 22248519954 ps, Illegal
    state bin illegal_err of coverpoint err_code_vals in covergroup

Job otp_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.otp_ctrl_csr_mem_rw_with_rand_reset.52262556928771512337235826397562646269812812473533740561600800254372771931324
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  Job ID: smart:ee90f923-a8fb-493b-b9ce-5667dc1deb5b
```
- Test otp_ctrl_same_csr_outstanding has 1 failures.
  - 15.otp_ctrl_same_csr_outstanding.23380734508043089078590676533226708826496139666352426764940043667273930977963
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest/run.log
```
  Job ID: smart:2456b1cf-a1f3-4082-aa88-7af564276e46
```
Job otp_ctrl-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test otp_ctrl_tl_intg_err has 1 failures.
  - 12.otp_ctrl_tl_intg_err.23011543028710345731125036637471604221184354073604340253451212059377503582172
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest/run.log
```
  Job ID: smart:6ec912a4-30f9-4739-85fe-318fb1d60ad2
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 1 failures:
- Test otp_ctrl_check_fail has 1 failures.
  - 39.otp_ctrl_check_fail.100301227491398607989342108504693178078173187851704409981716381837950720081889
    Line 264, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 169600114 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 169600114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```