OTP_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.810s	129.331us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.070s	1.504ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.250s	605.875us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.410s	1.413ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.960s	2.501ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.220s	1.692ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.250s	605.875us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	2.501ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.810s	550.702us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.370s	56.229us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.680s	615.549us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.810s	2.797ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	36.770s	6.466ms	10	10	100.00
		otp_ctrl_check_fail	1.651m	10.785ms	48	50	96.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.720s	5.441ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	49.260s	5.476ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	27.110s	1.194ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	47.050s	13.360ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.275m	9.846ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	52.770s	12.549ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	6.029m	137.534ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.940s	562.329us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.380s	376.085us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.050s	2.744ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.050s	2.744ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.070s	1.504ms	5	5	100.00
		otp_ctrl_csr_rw	2.250s	605.875us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	2.501ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.670s	1.841ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.070s	1.504ms	5	5	100.00
		otp_ctrl_csr_rw	2.250s	605.875us	20	20	100.00
		otp_ctrl_csr_aliasing	5.960s	2.501ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.670s	1.841ms	20	20	100.00
V2		TOTAL			1098	1101	99.73
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
		otp_ctrl_tl_intg_err	44.600s	19.285ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	44.600s	19.285ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_macro_errs	1.275m	9.846ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_macro_errs	1.275m	9.846ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.040s	8.504ms	200	200	100.00
		otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.810s	2.797ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.651m	10.785ms	48	50	96.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.657m	13.424ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.117m	142.850ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.720s	5.441ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.240s	1.869ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.275m	9.846ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.040s	3.114ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.955h	4.086s	93	100	93.00
V3		TOTAL			94	101	93.07
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.10983652670873488530992204526131296373369799001489022489730085477353793508268
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:714431a6-32e4-4807-b6cf-1b21afa7747e
```
  - 64.otp_ctrl_stress_all_with_rand_reset.29242041051104360181018949572348782204307400691146897382848277012505855117196
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c1785d96-7f0e-4f86-be83-9959a1431a9d
```
  - ... and 2 more failures.
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 6.otp_ctrl_stress_all_with_rand_reset.96012148306867252377416197573584252043019565390886733660710960879939553175384
    Line 26689, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 215082143141 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 215082143141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.otp_ctrl_stress_all_with_rand_reset.55523010426786078868075153869482986215351747995567509687709036224447280961958
    Line 10418, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 215059846640 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 215059846640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 2 failures:
- Test otp_ctrl_check_fail has 2 failures.
  - 11.otp_ctrl_check_fail.82954910312690877107236057650737792396223352581460717630592448001578395832413
    Line 279, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @  52029522 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @  52029522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.otp_ctrl_check_fail.1403191129567980011403406726154388841462837529462910064394047523117390765054
    Line 10309, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 3412204456 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 3412204456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1572) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@58440680) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.40835213739494733889360140567328334830883452000520994032865091072484462766098
    Line 17551, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 273456170027 ps: (otp_ctrl_scoreboard.sv:1572) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@58440680) { a_addr: 'h93240d78  a_data: 'h364dae98  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h89  a_opcode: 'h1  a_user: 'h26bbe  d_param: 'h0  d_source: 'h89  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 273456170027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1572) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@98063) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

49.otp_ctrl_test_access.71613291243747578471885622453645308460856236354938341302499140478168276175031
Line 6015, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 2246265791 ps: (otp_ctrl_scoreboard.sv:1572) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@98063) { a_addr: 'hb8625c64  a_data: 'hf68cbdb2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha6  a_opcode: 'h0  a_user: 'h2537d  d_param: 'h0  d_source: 'ha6  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 2246265791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test otp_ctrl has 1 failures.

cov_merge
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    features" in the VCS Release Notes
  
  
  Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
    -merge_across_libs needs special license feature VCSTools_Net
    Please check if your license server has feature VCSTools_Net available
  
  URG parallel failed in reporting step!
  Please fix the problem and use "urg_parallel_report.csh" script to re-generate the urg report.
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:220: cov_merge] Error 3

Job killed most likely because its dependent job failed. has 1 failures:
- Test otp_ctrl has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/cov_report/cov_report.log