OTP_CTRL Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.840s	119.619us	1	1	100.00
V1	smoke	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.340s	107.164us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.060s	556.918us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.400s	675.156us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.450s	1.156ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.710s	1.623ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.060s	556.918us	20	20	100.00
		otp_ctrl_csr_aliasing	3.450s	1.156ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.580s	516.099us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.160s	546.571us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.630s	815.574us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.700s	2.488ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	21.490s	2.885ms	10	10	100.00
		otp_ctrl_check_fail	23.530s	9.849ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.920s	3.750ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.156m	6.823ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	22.580s	713.461us	50	50	100.00
		otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	21.270s	5.921ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	29.450s	11.374ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.177m	7.663ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	4.442m	109.617ms	48	50	96.00
V2	intr_test	otp_ctrl_intr_test	2.120s	533.982us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.040s	422.643us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.230s	2.131ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.230s	2.131ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.340s	107.164us	5	5	100.00
		otp_ctrl_csr_rw	2.060s	556.918us	20	20	100.00
		otp_ctrl_csr_aliasing	3.450s	1.156ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.200s	219.296us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.340s	107.164us	5	5	100.00
		otp_ctrl_csr_rw	2.060s	556.918us	20	20	100.00
		otp_ctrl_csr_aliasing	3.450s	1.156ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.200s	219.296us	20	20	100.00
V2		TOTAL			1098	1101	99.73
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
		otp_ctrl_tl_intg_err	41.940s	18.318ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	41.940s	18.318ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_macro_errs	29.450s	11.374ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_macro_errs	29.450s	11.374ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.700s	6.749ms	200	200	100.00
		otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.700s	2.488ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	23.530s	9.849ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	41.370s	12.389ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.345m	35.395ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.920s	3.750ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	9.840s	631.491us	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	29.450s	11.374ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.470s	3.024ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.972h	4.163s	92	100	92.00
V3		TOTAL			93	101	92.08
		TOTAL			1332	1343	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.42	92.63	91.48	92.48	92.11	93.49	96.53	95.19

Failure Buckets

UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.106144090768868176366285035935575217660656586934336652551801796595391820640640
    Line 316, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2938172397 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2938172397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.otp_ctrl_stress_all_with_rand_reset.115558513805068578067758903393740695019439965395466571396878107510255170236904
    Line 410, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120127198235 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 120127198235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@24420572) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.13179788707926427238074401134283078954850712971531182019418344612266648595906
    Line 1180, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429032988747 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@24420572) { a_addr: 'h542b354c  a_data: 'hd65f0e4e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h0  a_user: 'h279e1  d_param: 'h0  d_source: 'h2  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 429032988747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@244240) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

22.otp_ctrl_stress_all.21765219678810343677579512501393537568027015952747840080570748549085950444152
Line 282, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1089303087 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@244240) { a_addr: 'hebf7f8d8  a_data: 'h332052c0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h62  a_opcode: 'h0  a_user: 'h2739f  d_param: 'h0  d_source: 'h62  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 1089303087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@101294) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

28.otp_ctrl_test_access.71554502645348052548562330383454504150556600698477994091305021464479375181376
Line 265, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 704937043 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@101294) { a_addr: 'h4ef4136c  a_data: 'h6ec5b1ec  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h40  a_opcode: 'h1  a_user: 'h26838  d_param: 'h0  d_source: 'h40  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 704937043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@965675) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

31.otp_ctrl_stress_all.39116465177046703095196396184778053198069346945982529534870502420903021051985
Line 311, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8004178108 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@965675) { a_addr: 'h57b5bbbc  a_data: 'hf7eba7e5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5a  a_opcode: 'h1  a_user: 'h25365  d_param: 'h0  d_source: 'h5a  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 8004178108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 50.otp_ctrl_stress_all_with_rand_reset.88027152791457118628271850063290754894565400019783752305303563442604797824407
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8f2fae9d-282e-4b38-a996-352d92adb73f
```
UVM_ERROR (otp_ctrl_scoreboard.sv:565) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr *bc*, csr_addr * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 60.otp_ctrl_stress_all_with_rand_reset.44084835663354415337371783309454796428014337281172276226322715565880898205835
    Line 1760, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1302411190220 ps: (otp_ctrl_scoreboard.sv:565) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (3857579454 [0xe5edfdbe] vs 2783555002 [0xa5e9adba]) mem read mismatch at TLUL addr 5bc43678, csr_addr 678
  UVM_INFO @ 1302411190220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 71.otp_ctrl_stress_all_with_rand_reset.29315163341019352028040622897910269774053120722229329741630756923495588218234
    Line 400, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 2449796943492 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 2449796943492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```