0dd29ab736| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 2.290s | 187.335us | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 2.200s | 570.155us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 13.510s | 7.434ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 5.820s | 2.025ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 3.660s | 100.527us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.200s | 570.155us | 20 | 20 | 100.00 |
| otp_ctrl_csr_aliasing | 5.820s | 2.025ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 1.680s | 516.296us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.920s | 531.369us | 5 | 5 | 100.00 |
| V1 | TOTAL | 64 | 116 | 55.17 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 0 | 1 | 0.00 | ||
| V2 | init_fail | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2 | partition_check | otp_ctrl_background_chks | 0 | 10 | 0.00 | ||
| otp_ctrl_check_fail | 0 | 50 | 0.00 | ||||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | partition_lock | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 0 | 50 | 0.00 | ||
| otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 0 | 50 | 0.00 | ||
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2 | test_access | otp_ctrl_test_access | 0 | 50 | 0.00 | ||
| V2 | stress_all | otp_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | otp_ctrl_intr_test | 2.080s | 610.805us | 50 | 50 | 100.00 |
| V2 | alert_test | otp_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 9.560s | 2.653ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 9.560s | 2.653ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 2.290s | 187.335us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.200s | 570.155us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 5.820s | 2.025ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.780s | 295.657us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 2.290s | 187.335us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.200s | 570.155us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 5.820s | 2.025ms | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.780s | 295.657us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1101 | 8.17 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | tl_intg_err | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| otp_ctrl_tl_intg_err | 25.940s | 18.543ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 25.940s | 18.543ms | 20 | 20 | 100.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| V3 | TOTAL | 0 | 101 | 0.00 | |||
| TOTAL | 174 | 1343 | 12.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 6 | 66.67 |
| V2 | 17 | 17 | 3 | 17.65 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 33.39 | 22.78 | 29.38 | 12.68 | 0.00 | 22.85 | 99.69 | 46.35 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 584 failures:
Test otp_ctrl_wake_up has 1 failures.
Test otp_ctrl_partition_walk has 1 failures.
Test otp_ctrl_init_fail has 183 failures.
0.otp_ctrl_init_fail.58346517188784296249532696497138713175568646045888750865081228976391725283434
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest/run.log
1.otp_ctrl_init_fail.109757743574156504419027121760740589976793502586472418604902426608230958662798
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest/run.log
... and 181 more failures.
Test otp_ctrl_parallel_lc_req has 48 failures.
0.otp_ctrl_parallel_lc_req.89848702983755578824218295470884621027202721967778015055981844342064671098584
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest/run.log
1.otp_ctrl_parallel_lc_req.10109576517752257710835548263331505877058843077852227885523806883498901102648
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest/run.log
... and 46 more failures.
Test otp_ctrl_dai_lock has 48 failures.
0.otp_ctrl_dai_lock.55474362389236678026378704885475412598214469435064190253694140858379206379250
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log
1.otp_ctrl_dai_lock.59776042466058152849387151894932870268570815930923046225227096104540206584708
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest/run.log
... and 46 more failures.
... and 12 more tests.
Job killed most likely because its dependent job failed. has 584 failures:
Test otp_ctrl_smoke has 8 failures.
0.otp_ctrl_smoke.102198992427255488122853290504243888273545713920580082021947467396297138212633
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest/run.log
1.otp_ctrl_smoke.8984252485813124087985529096686665753796401833711621994568175542891294327936
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest/run.log
... and 6 more failures.
Test otp_ctrl_low_freq_read has 1 failures.
Test otp_ctrl_background_chks has 8 failures.
0.otp_ctrl_background_chks.24836259200221993863677950361014569322338213429173074632232266860096238375667
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest/run.log
1.otp_ctrl_background_chks.52621366249228239638186601704722015660880984229533783478188094126281762076388
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest/run.log
... and 6 more failures.
Test otp_ctrl_parallel_lc_esc has 173 failures.
0.otp_ctrl_parallel_lc_esc.37205291019325536692799309652757909106714745280006922226511243583616465415098
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest/run.log
1.otp_ctrl_parallel_lc_esc.49998508065288868612445631476143169017656728930835047096239623309554628209307
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest/run.log
... and 171 more failures.
Test otp_ctrl_dai_errs has 48 failures.
0.otp_ctrl_dai_errs.49870060850496175265896974500108067520570560843340640539333228648579706080226
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log
1.otp_ctrl_dai_errs.91933171089951197003314920542747060330178737711501640761122486655050286632943
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest/run.log
... and 46 more failures.
... and 12 more tests.
Offending '(cio_test_en_o == *)' has 1 failures:
8.otp_ctrl_csr_mem_rw_with_rand_reset.82070315486881715308451571964245581994941180795479490543935139352950132332153
Line 275, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 107824629 ps: (otp_ctrl_if.sv:269) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 107824629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---