OTP_CTRL Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	59.765us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.620s	359.907us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.310s	697.921us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.190s	6.978ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.330s	3.151ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.140s	403.472us	10	20	50.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.310s	697.921us	20	20	100.00
		otp_ctrl_csr_aliasing	7.330s	3.151ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.360s	70.825us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.510s	549.266us	5	5	100.00
V1		TOTAL			106	116	91.38
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.480s	3.077ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.460s	3.232ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	26.450s	2.083ms	10	10	100.00
		otp_ctrl_check_fail	2.410m	15.745ms	47	50	94.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.640s	342.067us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.047m	18.794ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.040s	11.430ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.314m	22.247ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	51.900s	22.158ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.166m	31.902ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.340m	46.962ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.970s	555.504us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.450s	387.451us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.870s	2.520ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.870s	2.520ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.620s	359.907us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	697.921us	20	20	100.00
		otp_ctrl_csr_aliasing	7.330s	3.151ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.190s	1.854ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.620s	359.907us	5	5	100.00
		otp_ctrl_csr_rw	2.310s	697.921us	20	20	100.00
		otp_ctrl_csr_aliasing	7.330s	3.151ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.190s	1.854ms	20	20	100.00
V2		TOTAL			1098	1101	99.73
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.300s	20.221ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.300s	20.221ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_macro_errs	51.900s	22.158ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_macro_errs	51.900s	22.158ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.720s	4.275ms	200	200	100.00
		otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.460s	3.232ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.410m	15.745ms	47	50	94.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	47.070s	12.766ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.430m	154.702ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.640s	342.067us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.560s	7.006ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	51.900s	22.158ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.640s	3.012ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.946h	1.617s	63	100	63.00
V3		TOTAL			64	101	63.37
		TOTAL			1293	1343	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.18	91.53	89.76	89.32	72.73	91.55	96.26	93.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 22 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 22 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.99047628664415170363274463021340716709278240382716149176067234225874005402591
    Line 50072, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 804899564387 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 804899564387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.85452239650695251831506844290302013506560933545042821201766110802516358260286
    Line 83302, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 483201626962 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 483201626962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.

UVM_ERROR (cip_base_vseq.sv:719) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 19 failures:

Test otp_ctrl_csr_mem_rw_with_rand_reset has 10 failures.

0.otp_ctrl_csr_mem_rw_with_rand_reset.8723858406647472945952536720676925007433722144623947819681587819520491896535
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  72953586 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  72953586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otp_ctrl_csr_mem_rw_with_rand_reset.1129482093616805026602850948523476023572891528502512792378865904236908662106
Line 278, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1181025713 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1181025713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test otp_ctrl_stress_all_with_rand_reset has 9 failures.

16.otp_ctrl_stress_all_with_rand_reset.115036342053032452298812810253250457101221573861165170188481184046466862690328
Line 1148, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1666772515058 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1666772515058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.otp_ctrl_stress_all_with_rand_reset.9253728343801334940179818462456320307504481197235716161818295224168543710189
Line 15930, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 466002182023 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 466002182023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 3 failures:
- Test otp_ctrl_check_fail has 3 failures.
  - 9.otp_ctrl_check_fail.47189830780138303773276541340075958858388318769127935869073832865793077248092
    Line 2726, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 222530455 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 222530455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otp_ctrl_check_fail.60444789980000778427115579050130330270204911848425414044454280061719252602419
    Line 13178, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 431816429 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 431816429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 34.otp_ctrl_stress_all_with_rand_reset.50444202905028424477293404256371559412875377242874462272969275893673151401211
    Line 27301, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 366779664127 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 366779664127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.otp_ctrl_stress_all_with_rand_reset.41829793037745077795891433858351349219876218893741960748997626975555266511837
    Line 24257, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 428837663254 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 428837663254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 36.otp_ctrl_stress_all_with_rand_reset.19654620732042317770160069101942656991378585191789394911443137836578639910873
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a99185e2-248b-4ffe-8543-c36f6987ce28
```
  - 73.otp_ctrl_stress_all_with_rand_reset.81125225820410350048400782450374206654709991014744459674854153566161298981854
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:39e15604-cf4e-4c27-80b4-dfcab985ce94
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

26.otp_ctrl_stress_all_with_rand_reset.62307849128008930637058389645738341309930689456372665536485979807287176124847
Line 4936, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 8671001311 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 8671072741 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8671172743 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8671901329 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 8671929901 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@35528816) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.otp_ctrl_stress_all_with_rand_reset.45469262380950760260798992189876422352135241246264250033217853403617934684366
    Line 76428, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 309861157663 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@35528816) { a_addr: 'h61348930  a_data: 'hdf139719  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6b  a_opcode: 'h0  a_user: 'h2525e  d_param: 'h0  d_source: 'h6b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 309861157663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```