OTP_CTRL Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	126.264us	1	1	100.00
V1	smoke	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.790s	1.471ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.920s	666.249us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.760s	6.836ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.030s	809.901us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.510s	1.692ms	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.920s	666.249us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	809.901us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.590s	507.587us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.490s	536.314us	5	5	100.00
V1		TOTAL			113	116	97.41
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.560s	502.229us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.950s	2.297ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	45.660s	4.459ms	10	10	100.00
		otp_ctrl_check_fail	44.990s	5.809ms	45	50	90.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.740s	4.874ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.797m	4.424ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.520s	14.000ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	58.270s	17.790ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	49.200s	2.083ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.109m	15.186ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	17.567m	309.490ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.090s	526.394us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.030s	209.943us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.620s	2.544ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.620s	2.544ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.790s	1.471ms	5	5	100.00
		otp_ctrl_csr_rw	2.920s	666.249us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	809.901us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	1.432ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.790s	1.471ms	5	5	100.00
		otp_ctrl_csr_rw	2.920s	666.249us	20	20	100.00
		otp_ctrl_csr_aliasing	7.030s	809.901us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.880s	1.432ms	20	20	100.00
V2		TOTAL			1095	1101	99.46
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.660s	2.412ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.660s	2.412ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_macro_errs	49.200s	2.083ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_macro_errs	49.200s	2.083ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	41.610s	15.977ms	200	200	100.00
		otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.950s	2.297ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	44.990s	5.809ms	45	50	90.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	57.240s	28.822ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.643m	15.585ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.740s	4.874ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	46.550s	5.155ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	49.200s	2.083ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.510s	3.122ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.942h	2.084s	65	100	65.00
V3		TOTAL			66	101	65.35
		TOTAL			1299	1343	96.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.48	91.65	90.25	89.67	73.30	91.86	96.33	93.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 19 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 19 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.23757386967439962256947248220480010632602923844163322872278479077003311287173
    Line 5164, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45359397533 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 45359397533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.13081536546915225609081866573738603598819781037018125446690378738932946791137
    Line 72147, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22418222836 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 22418222836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:719) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 13 failures:

Test otp_ctrl_csr_mem_rw_with_rand_reset has 3 failures.

6.otp_ctrl_csr_mem_rw_with_rand_reset.87144116838912268302779426348579432607608037766134895967294253600070653207522
Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  73125308 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  73125308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otp_ctrl_csr_mem_rw_with_rand_reset.19936555008961121120708035055506313986469216743124602245195426772715778545626
Line 268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  37480366 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  37480366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otp_ctrl_stress_all_with_rand_reset has 10 failures.

16.otp_ctrl_stress_all_with_rand_reset.77059936896941982059303923832585632151659895639777331995370051497461104515706
Line 34299, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 212043136991 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 212043136991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.otp_ctrl_stress_all_with_rand_reset.61259601215009095063137277839127704384492980357118534570215820331125570449499
Line 69716, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5020145769141 ps: (cip_base_vseq.sv:719) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5020145769141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 5 failures:
- Test otp_ctrl_check_fail has 5 failures.
  - 0.otp_ctrl_check_fail.45974956777786760421681914904420883342544979535863013597861225905361094831014
    Line 4374, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 1363799890 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 1363799890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.otp_ctrl_check_fail.95600312963520300656660566048108297403965561650580968271170861853715819252705
    Line 12872, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 501224899 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 501224899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

46.otp_ctrl_stress_all_with_rand_reset.102607684152586100299559898786893806545916600136032756961025258952748623761303
Line 2805, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 722572182 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 722832182 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 722952182 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 723572182 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 723652182 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

57.otp_ctrl_stress_all_with_rand_reset.31196271538890734557014399991066870667174933407438220042611580341106593841586
Line 92312, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 690991526024 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 690992106024 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 690992126024 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 691021066024 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 691021086024 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.12145046248389803820897645085084190482578648448380307088504489859429483808479
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ae0b0da4-a833-49ed-ae81-d9572e5c83f8
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@416037) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.50852370403498792575244961780373110449700886070389606657398117237607235538856
    Line 14021, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 975500120 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@416037) { a_addr: 'h74efa99c  a_data: 'heffc4185  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb4  a_opcode: 'h1  a_user: 'h24129  d_param: 'h0  d_source: 'hb4  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 975500120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 42.otp_ctrl_stress_all.76197007305889916946724338865335226158882239819380436445761848444159995111199
    Line 1331, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 125502187 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 125502187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 50.otp_ctrl_stress_all_with_rand_reset.61410888439925632080170474966754241578287423145161970983572752154696694397513
    Line 103066, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 382885420685 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 382885420685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 94.otp_ctrl_stress_all_with_rand_reset.34860270160377349720625309104260895798559910004676781645023289568780858556459
    Line 37188, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65463403064 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 65463403064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```