a9c19f09f3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 13.000s | 276.454us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 4.000s | 49.859us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 8.000s | 12.650us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 400.413us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 7.000s | 75.185us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 8.000s | 54.607us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 8.000s | 12.650us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 7.000s | 75.185us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.750m | 16.434ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.683m | 4.022ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 13.000s | 163.478us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 3.733m | 23.091ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 8.000s | 14.661us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 7.000s | 17.357us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 9.000s | 153.600us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 9.000s | 153.600us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 4.000s | 49.859us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 8.000s | 12.650us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 75.185us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 55.915us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 4.000s | 49.859us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 8.000s | 12.650us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 7.000s | 75.185us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 55.915us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 7.000s | 193.331us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 2.000s | 36.066us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 7.000s | 193.331us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 32.850m | 92.773ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 513 | 520 | 98.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
1.pattgen_stress_all_with_rand_reset.91046214269203484303837780942146920811359776155222771994707046072025374937758
Line 871, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 328909545143 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
29.pattgen_stress_all_with_rand_reset.45316256554801332268426600221117179241245405896947727466064898644936752530403
Line 395, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1505630961 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
14.pattgen_stress_all_with_rand_reset.66741995702721424525975273043047233156464364858963352674170021042950278310136
Line 1265, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 118105158173 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @17037