PWM Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	523.867us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	63.036us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	50.111us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	13.000s	464.005us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	102.680us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	27.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	50.111us	20	20	100.00
		pwm_csr_aliasing	4.000s	102.680us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	pulse	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	blink	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	heartbeat	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	resolution	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	multi_channel	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	polarity	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	phase	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	lowpower	pwm_rand_output	1.100m	21.430ms	48	50	96.00
V2	perf	pwm_perf	54.000s	43.747ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.150m	54.612ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	46.585us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	23.553us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	444.419us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	444.419us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	63.036us	5	5	100.00
		pwm_csr_rw	3.000s	50.111us	20	20	100.00
		pwm_csr_aliasing	4.000s	102.680us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	34.665us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	63.036us	5	5	100.00
		pwm_csr_rw	3.000s	50.111us	20	20	100.00
		pwm_csr_aliasing	4.000s	102.680us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	34.665us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	559.958us	20	20	100.00
		pwm_sec_cm	3.000s	398.978us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	559.958us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	99.46	99.01	99.84	94.72	94.92	--	100.00	99.34

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test pwm_perf has 1 failures.

16.pwm_perf.205710337
Line 334, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_rand_output has 2 failures.

33.pwm_rand_output.3723198515
Line 356, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/33.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.pwm_rand_output.4031132546
Line 2852, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

26.pwm_stress_all.3398752271
Line 3557181, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log

  UVM_ERROR @ 50470364410 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 50470364410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.pwm_stress_all.667317442
Line 30761, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/41.pwm_stress_all/latest/run.log

  UVM_ERROR @ 161517801650 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 161517801650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---