PWM Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 14.000s 2.035ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 12.000s 21.465us 5 5 100.00
V1 csr_rw pwm_csr_rw 12.000s 106.998us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 12.000s 331.513us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 92.020us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 13.000s 69.839us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 12.000s 106.998us 20 20 100.00
pwm_csr_aliasing 4.000s 92.020us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 pulse pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 blink pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 heartbeat pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 resolution pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 multi_channel pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 polarity pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 phase pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 lowpower pwm_rand_output 1.433m 14.001ms 48 50 96.00
V2 perf pwm_perf 53.000s 11.936ms 50 50 100.00
V2 stress_all pwm_stress_all 4.533m 74.750ms 50 50 100.00
V2 alert_test pwm_alert_test 12.000s 15.400us 50 50 100.00
V2 intr_test pwm_intr_test 12.000s 12.522us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 9.000s 188.380us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 9.000s 188.380us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 12.000s 21.465us 5 5 100.00
pwm_csr_rw 12.000s 106.998us 20 20 100.00
pwm_csr_aliasing 4.000s 92.020us 5 5 100.00
pwm_same_csr_outstanding 8.000s 81.173us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 12.000s 21.465us 5 5 100.00
pwm_csr_rw 12.000s 106.998us 20 20 100.00
pwm_csr_aliasing 4.000s 92.020us 5 5 100.00
pwm_same_csr_outstanding 8.000s 81.173us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err pwm_tl_intg_err 19.000s 848.232us 20 20 100.00
pwm_sec_cm 7.000s 35.335us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 19.000s 848.232us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 418 420 99.52

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.13 99.07 98.34 99.84 94.21 94.92 -- 100.00 99.34

Failure Buckets

Past Results