PWM Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	3.909ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	35.452us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	212.841us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	680.101us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	172.933us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	295.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	212.841us	20	20	100.00
		pwm_csr_aliasing	5.000s	172.933us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	pulse	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	blink	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	resolution	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	polarity	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	phase	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.183m	10.942ms	50	50	100.00
V2	perf	pwm_perf	51.000s	43.750ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.350m	284.604ms	48	50	96.00
V2	alert_test	pwm_alert_test	7.000s	36.867us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	21.059us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	131.632us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	131.632us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	35.452us	5	5	100.00
		pwm_csr_rw	4.000s	212.841us	20	20	100.00
		pwm_csr_aliasing	5.000s	172.933us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	82.420us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	35.452us	5	5	100.00
		pwm_csr_rw	4.000s	212.841us	20	20	100.00
		pwm_csr_aliasing	5.000s	172.933us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	82.420us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	220.262us	20	20	100.00
		pwm_sec_cm	3.000s	43.510us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	220.262us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	99.45	99.01	99.84	94.55	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

16.pwm_stress_all.21473097483986669605444548145892731793375099481083993962419814241067691960568
Line 6444, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_stress_all/latest/run.log

  UVM_ERROR @ 45892448539 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 45892448539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.pwm_stress_all.110414425174178632311460097545220321452992461481873547042864203441570696679000
Line 620, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log

  UVM_ERROR @ 30070658089 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 30070658089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---