PWM Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 5.000s 2.046ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 2.000s 62.214us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 20.589us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 1.248ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 410.574us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 101.136us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 20.589us 20 20 100.00
pwm_csr_aliasing 3.000s 410.574us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 pulse pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 blink pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 heartbeat pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 resolution pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 multi_channel pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 polarity pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 phase pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 lowpower pwm_rand_output 1.583m 21.006ms 49 50 98.00
V2 perf pwm_perf 51.000s 10.716ms 50 50 100.00
V2 stress_all pwm_stress_all 4.033m 543.949ms 46 50 92.00
V2 alert_test pwm_alert_test 3.000s 15.668us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 14.193us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 7.000s 174.227us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 7.000s 174.227us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 2.000s 62.214us 5 5 100.00
pwm_csr_rw 3.000s 20.589us 20 20 100.00
pwm_csr_aliasing 3.000s 410.574us 5 5 100.00
pwm_same_csr_outstanding 4.000s 108.668us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 2.000s 62.214us 5 5 100.00
pwm_csr_rw 3.000s 20.589us 20 20 100.00
pwm_csr_aliasing 3.000s 410.574us 5 5 100.00
pwm_same_csr_outstanding 4.000s 108.668us 20 20 100.00
V2 TOTAL 285 290 98.28
V2S tl_intg_err pwm_tl_intg_err 6.000s 2.058ms 20 20 100.00
pwm_sec_cm 2.000s 142.494us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 2.058ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 415 420 98.81

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.33 99.31 98.77 99.80 94.76 94.92 -- 100.00 99.01

Failure Buckets

Past Results