01a208901a
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 5.000s | 2.046ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 62.214us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 20.589us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 1.248ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 410.574us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 101.136us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 20.589us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 3.000s | 410.574us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 1.583m | 21.006ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 51.000s | 10.716ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.033m | 543.949ms | 46 | 50 | 92.00 |
V2 | alert_test | pwm_alert_test | 3.000s | 15.668us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 14.193us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 174.227us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 174.227us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 62.214us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 20.589us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 410.574us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 108.668us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 62.214us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 20.589us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 410.574us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 108.668us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 285 | 290 | 98.28 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 2.058ms | 20 | 20 | 100.00 |
pwm_sec_cm | 2.000s | 142.494us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 2.058ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 415 | 420 | 98.81 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.33 | 99.31 | 98.77 | 99.80 | 94.76 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 5 failures:
22.pwm_stress_all.13319209288235724859395837659274922401430443007637537725907318559455436094064
Line 2886, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/22.pwm_stress_all/latest/run.log
UVM_ERROR @ 16607916676 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 16607916676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.pwm_stress_all.100824018949608820821882449525389884897879472268760439857323853659184488379282
Line 582, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/35.pwm_stress_all/latest/run.log
UVM_ERROR @ 27581025311 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 27581025311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
29.pwm_rand_output.114912696849169818143592670486949479364855034798191057585570449373431372119960
Line 192979, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/29.pwm_rand_output/latest/run.log
UVM_ERROR @ 42152864861 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 42152864861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---