PWM Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	2.033ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	23.609us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	16.063us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	1.524ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	3.000s	160.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	101.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	16.063us	20	20	100.00
		pwm_csr_aliasing	3.000s	160.348us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	pulse	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	blink	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	resolution	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	polarity	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	phase	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.083m	43.744ms	49	50	98.00
V2	perf	pwm_perf	50.000s	10.828ms	49	50	98.00
V2	stress_all	pwm_stress_all	6.433m	328.100ms	47	50	94.00
V2	alert_test	pwm_alert_test	3.000s	15.162us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	11.252us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	55.244us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	55.244us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	23.609us	5	5	100.00
		pwm_csr_rw	3.000s	16.063us	20	20	100.00
		pwm_csr_aliasing	3.000s	160.348us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	204.386us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	23.609us	5	5	100.00
		pwm_csr_rw	3.000s	16.063us	20	20	100.00
		pwm_csr_aliasing	3.000s	160.348us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	204.386us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	89.305us	20	20	100.00
		pwm_sec_cm	3.000s	40.338us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	89.305us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.68	99.59	99.26	99.96	95.58	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

18.pwm_stress_all.8396980921095352795081452973319249654283218590630386765583047309579500264629
Line 2894, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/18.pwm_stress_all/latest/run.log

  UVM_ERROR @ 137577311247 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 137577311247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.pwm_stress_all.3614895744993206932884643828421649497216783165659618722880791869519234740157
Line 554, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_stress_all/latest/run.log

  UVM_ERROR @ 49598523184 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 49598523184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_perf has 1 failures.
  - 40.pwm_perf.80680578749908286146321027277320842596479584797972478830953756266435705666141
    Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/40.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwm_rand_output has 1 failures.
  - 41.pwm_rand_output.114916177294010507727505817742109443208845331349829495932195790892695872212509
    Line 404, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/41.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```