PWM Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	10.000s	2.036ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	14.433us	5	5	100.00
V1	csr_rw	pwm_csr_rw	8.000s	17.333us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	276.680us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	81.133us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	12.000s	66.053us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	8.000s	17.333us	20	20	100.00
		pwm_csr_aliasing	4.000s	81.133us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	pulse	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	blink	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	resolution	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	polarity	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	phase	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.133m	21.006ms	50	50	100.00
V2	perf	pwm_perf	53.000s	65.634ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.300m	449.880ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	19.954us	50	50	100.00
V2	intr_test	pwm_intr_test	15.000s	23.299us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	112.306us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	112.306us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	14.433us	5	5	100.00
		pwm_csr_rw	8.000s	17.333us	20	20	100.00
		pwm_csr_aliasing	4.000s	81.133us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	71.806us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	14.433us	5	5	100.00
		pwm_csr_rw	8.000s	17.333us	20	20	100.00
		pwm_csr_aliasing	4.000s	81.133us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	71.806us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	68.884us	20	20	100.00
		pwm_sec_cm	3.000s	143.575us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	68.884us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.20	99.17	98.52	99.76	94.48	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

15.pwm_stress_all.10465087719217444463003296588871436635142497241986683594127351769264654583412
Line 1682937, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_stress_all/latest/run.log

  UVM_ERROR @ 126423993698 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 126423993698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.pwm_stress_all.67852103736143158295973065665559352920240354160286739191682033932036068613956
Line 169861, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/33.pwm_stress_all/latest/run.log

  UVM_ERROR @ 40484414036 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 40484414036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 28.pwm_perf.100448638504119215502694103726042131822881709741313649453704512474621965078563
    Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/28.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```