PWM Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	3.003ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	84.450us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	15.594us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	669.353us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	37.820us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	88.743us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	15.594us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.820us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	pulse	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	blink	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	resolution	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	polarity	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	phase	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.850m	10.717ms	50	50	100.00
V2	perf	pwm_perf	51.000s	10.831ms	48	50	96.00
V2	stress_all	pwm_stress_all	5.633m	149.975ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	55.038us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	14.937us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	487.098us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	487.098us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	84.450us	5	5	100.00
		pwm_csr_rw	3.000s	15.594us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.820us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	243.447us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	84.450us	5	5	100.00
		pwm_csr_rw	3.000s	15.594us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.820us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	243.447us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	536.421us	20	20	100.00
		pwm_sec_cm	12.000s	36.915us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	536.421us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.29	99.31	98.77	99.80	94.59	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_perf has 2 failures.
  - 5.pwm_perf.12040139483140911484942680393550635561082250438201608607113566304112854400934
    Line 325, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.pwm_perf.1213601675455809495934755134879600625686222695215346165016859235730995633615
    Line 379, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

8.pwm_stress_all.99789917468876708269741662789043052776392330390167669439784648758623838086521
Line 1446409, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/8.pwm_stress_all/latest/run.log

  UVM_ERROR @ 30981973891 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 30981973891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.pwm_stress_all.58982023966099685182835422225161046040538849647350768325130243834518229599377
Line 656, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_stress_all/latest/run.log

  UVM_ERROR @ 20995374430 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 20995374430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---