302b24f3c6
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 5.000s | 1.065ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 27.169us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 50.021us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 9.000s | 315.014us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 84.802us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 52.620us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 50.021us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 3.000s | 84.802us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 58.000s | 41.996ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 52.000s | 21.002ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.033m | 76.567ms | 48 | 50 | 96.00 |
V2 | alert_test | pwm_alert_test | 2.000s | 40.237us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 46.594us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 177.803us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 177.803us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 27.169us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 50.021us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 84.802us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 3.000s | 465.339us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 27.169us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 50.021us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 84.802us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 3.000s | 465.339us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 227.834us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 91.331us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 227.834us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.42 | 99.38 | 98.89 | 99.92 | 94.86 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
Test pwm_stress_all has 2 failures.
24.pwm_stress_all.93310110160528309773702246809874658435955918999430812757052938885960304071453
Line 1798549, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_stress_all/latest/run.log
UVM_ERROR @ 22598551914 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 22598551914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.pwm_stress_all.96241702049991054728565429308464589987816958516371272574900712110464534000445
Line 1274, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/32.pwm_stress_all/latest/run.log
UVM_ERROR @ 153608937864 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 153608937864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_rand_output has 1 failures.
42.pwm_rand_output.76595945130507608238935958943704971652186697706865188051724227851567868906200
Line 244468, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/42.pwm_rand_output/latest/run.log
UVM_ERROR @ 19906239673 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 19906239673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---