fdfa12db04| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 511.355us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 20.626us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 50.297us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 2.548ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 123.429us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 54.352us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 50.297us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 123.429us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 3.383m | 95.428ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 50.000s | 11.173ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.300m | 1.058s | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 14.999us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 42.089us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 149.398us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 149.398us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 20.626us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 50.297us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 123.429us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 39.416us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 20.626us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 50.297us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 123.429us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 39.416us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 391.501us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 77.017us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 391.501us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 417 | 420 | 99.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.27 | 99.24 | 98.65 | 99.88 | 94.48 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
27.pwm_rand_output.25961191880222359361519632662012171538810514829084041568227121659008003313685
Line 402, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/27.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.pwm_rand_output.86452373515882252322951151103740645469043396704520355942572889139673199057733
Line 402, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
5.pwm_stress_all.99673838892596574898753949424554054651536198934401321956348033561140696506508
Line 379437, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_stress_all/latest/run.log
UVM_ERROR @ 86063813812 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 86063813812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---