PWM Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	1.066ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	46.063us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	22.261us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	1.265ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	3.000s	116.873us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	21.494us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	22.261us	20	20	100.00
		pwm_csr_aliasing	3.000s	116.873us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	pulse	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	blink	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	resolution	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	polarity	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	phase	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.067m	21.880ms	50	50	100.00
V2	perf	pwm_perf	51.000s	10.610ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.650m	76.568ms	48	50	96.00
V2	alert_test	pwm_alert_test	9.000s	16.736us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	14.927us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	133.866us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	133.866us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	46.063us	5	5	100.00
		pwm_csr_rw	3.000s	22.261us	20	20	100.00
		pwm_csr_aliasing	3.000s	116.873us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	189.830us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	46.063us	5	5	100.00
		pwm_csr_rw	3.000s	22.261us	20	20	100.00
		pwm_csr_aliasing	3.000s	116.873us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	189.830us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	173.860us	20	20	100.00
		pwm_sec_cm	3.000s	45.700us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	173.860us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.58	99.62	99.32	99.96	95.03	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

34.pwm_stress_all.15823778016121707053026080371727128519367882856157509260064717625588551563962
Line 2530, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log

  UVM_ERROR @ 84973424699 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 84973424699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.pwm_stress_all.79659913042282439295868954009831566867286202840816525019840477269537885963339
Line 655, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_stress_all/latest/run.log

  UVM_ERROR @ 63616931861 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 63616931861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 38.pwm_perf.63246337229983182450980747832931378877922997016416146011486241287172888701474
    Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```