PWM Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	7.000s	516.367us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	18.900us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	16.499us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	3.709ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	37.673us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	54.557us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	16.499us	20	20	100.00
		pwm_csr_aliasing	4.000s	37.673us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	pulse	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	blink	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	resolution	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	polarity	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	phase	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.900m	174.992ms	49	50	98.00
V2	perf	pwm_perf	52.000s	150.001ms	48	50	96.00
V2	stress_all	pwm_stress_all	5.700m	12.538ms	46	50	92.00
V2	alert_test	pwm_alert_test	7.000s	164.893us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	80.979us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	5.000s	227.668us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	5.000s	227.668us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	18.900us	5	5	100.00
		pwm_csr_rw	3.000s	16.499us	20	20	100.00
		pwm_csr_aliasing	4.000s	37.673us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	342.914us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	18.900us	5	5	100.00
		pwm_csr_rw	3.000s	16.499us	20	20	100.00
		pwm_csr_aliasing	4.000s	37.673us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	342.914us	20	20	100.00
V2		TOTAL			283	290	97.59
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	268.680us	20	20	100.00
		pwm_sec_cm	3.000s	36.101us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	268.680us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			413	420	98.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	99.55	99.20	99.92	95.00	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:

Test pwm_stress_all has 4 failures.

7.pwm_stress_all.46977128719516669128703863479649161008790948967377176180205770158928431121769
Line 7539, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_stress_all/latest/run.log

  UVM_ERROR @ 177065117329 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 177065117329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.pwm_stress_all.51963243903991982341386930674675620889159461767225674427668172199897264092444
Line 39968, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/12.pwm_stress_all/latest/run.log

  UVM_ERROR @ 131276273400 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 131276273400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test pwm_rand_output has 1 failures.

0.pwm_rand_output.41366392417440718844153451636507975042000281629423589564904844554536616288838
Line 12672, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_perf has 2 failures.

24.pwm_perf.58925114570128699052377828860582973454596357337141425934896313435518753254246
Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.pwm_perf.10434699580751663680688619521540496578900485203831028314938372462489876114960
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/27.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---