PWM Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	515.118us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	35.952us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	49.642us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	3.421ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	403.014us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	56.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	49.642us	20	20	100.00
		pwm_csr_aliasing	4.000s	403.014us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	pulse	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	blink	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	resolution	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	polarity	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	phase	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.583m	12.808ms	50	50	100.00
V2	perf	pwm_perf	51.000s	10.940ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.550m	262.497ms	48	50	96.00
V2	alert_test	pwm_alert_test	12.000s	18.223us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	44.252us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	50.608us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	50.608us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	35.952us	5	5	100.00
		pwm_csr_rw	3.000s	49.642us	20	20	100.00
		pwm_csr_aliasing	4.000s	403.014us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	37.242us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	35.952us	5	5	100.00
		pwm_csr_rw	3.000s	49.642us	20	20	100.00
		pwm_csr_aliasing	4.000s	403.014us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	37.242us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	129.773us	20	20	100.00
		pwm_sec_cm	8.000s	101.270us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	129.773us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.45	99.41	98.95	99.88	94.96	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

24.pwm_stress_all.7041710088632513181885415294714639989152594553504494779968493061763849371562
Line 81068, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_stress_all/latest/run.log

  UVM_ERROR @ 65804445749 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 65804445749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.pwm_stress_all.37321532262135353787250805057528638773029933550520989833963525767419525680104
Line 898, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_stress_all/latest/run.log

  UVM_ERROR @ 127987317628 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 127987317628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 24.pwm_perf.55345245465242340180223326595449006064246154139779521649354221079906827522828
    Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```