PWRMGR Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	30.569us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	28.804us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.420s	310.732us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	40.995us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.200s	56.118us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	40.995us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.490s	207.680us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.490s	207.680us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.890s	25.855us	50	50	100.00
		pwrmgr_lowpower_invalid	0.920s	196.722us	49	50	98.00
V2	reset	pwrmgr_reset	1.330s	68.318us	50	50	100.00
		pwrmgr_reset_invalid	1.190s	92.420us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.330s	68.318us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.780s	236.291us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.770s	316.200us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.980s	90.345us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	12.540s	2.731ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	19.935us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.460s	184.972us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.460s	184.972us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	28.804us	5	5	100.00
		pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	40.995us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	47.953us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	28.804us	5	5	100.00
		pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	40.995us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	47.953us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.670s	201.595us	20	20	100.00
		pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.670s	201.595us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.070s	830.080us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.380s	802.016us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.070s	115.766us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.830s	28.924us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.000s	685.619us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.790s	81.193us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.900s	41.458us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.860s	229.598us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	25.932us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.830s	11.202ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			1066	1070	99.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.21	96.58	99.44	96.00	96.27	100.00	99.02

Failure Buckets

• Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 3.pwrmgr_stress_all_with_rand_reset.1851245170
      Line 6808, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 52816747113 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
        UVM_INFO @ 52816747113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 8.pwrmgr_stress_all_with_rand_reset.1608426135
      Line 3131, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 22427839932 ps: (pwrmgr.sv:160) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 22427839932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 46.pwrmgr_lowpower_invalid.2264764890
      Line 217, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  34012870 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  34012870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 46.pwrmgr_stress_all_with_rand_reset.2601059168
      Line 7106, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12981500217 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 12981500217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.20_19.35.59
• 2023.05.19_16.17.45
• 2023.05.18_19.19.37
• 2023.05.17_18.03.58
• 2023.05.16_19.27.31
• 2023.05.15_18.45.06
• 2023.05.14_18.13.20