PWRMGR Simulation Results

Wednesday September 06 2023 19:02:37 UTC

GitHub Revision: `60526f8d1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 131978952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	31.195us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	34.063us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.650s	1.112ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	75.572us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.240s	50.924us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	75.572us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.560s	235.633us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.560s	235.633us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.780s	32.852us	50	50	100.00
		pwrmgr_lowpower_invalid	0.860s	42.724us	50	50	100.00
V2	reset	pwrmgr_reset	1.230s	72.370us	50	50	100.00
		pwrmgr_reset_invalid	1.060s	78.513us	0	50	0.00
V2	main_power_glitch_reset	pwrmgr_reset	1.230s	72.370us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.640s	270.741us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.510s	259.369us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.990s	62.014us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.180s	2.481ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.770s	20.474us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.540s	136.238us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.540s	136.238us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	34.063us	5	5	100.00
		pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	75.572us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	67.876us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	34.063us	5	5	100.00
		pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	75.572us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	67.876us	20	20	100.00
V2		TOTAL			490	540	90.74
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.760s	201.435us	20	20	100.00
		pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.760s	201.435us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.150s	780.864us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.120s	801.666us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	91.259us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	29.965us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.160s	638.763us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	50.384us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.890s	39.086us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.570s	283.519us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	52.148us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	42.220s	8.968ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1018	1070	95.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.77	98.22	96.58	99.44	74.00	96.32	100.00	98.85

Failure Buckets

Offending '(fast_state == FastPwrStateRomCheckGood)' has 50 failures:

Test pwrmgr_reset_invalid has 50 failures.

0.pwrmgr_reset_invalid.3448020355
Line 253, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @ 117218797 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @ 117218797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_reset_invalid.4052671889
Line 253, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  86106645 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  86106645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_FATAL (cip_base_vseq.sv:99) [pwrmgr_common_vseq] wait timeout occurred! has 2 failures:

Test pwrmgr_stress_all_with_rand_reset has 2 failures.

2.pwrmgr_stress_all_with_rand_reset.2351709496
Line 686, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10134913336 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 10134913336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.pwrmgr_stress_all_with_rand_reset.2420155991
Line 3243, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16529739891 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 16529739891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---