ROM_CTRL Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	35.570s	14.913ms	46	50	92.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.190s	1.943ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.020s	4.260ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.890s	2.901ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.950s	1.593ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.830s	2.100ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.020s	4.260ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.950s	1.593ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.220s	4.114ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.240s	4.392ms	5	5	100.00
V1		TOTAL			111	115	96.52
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	16.100s	13.297ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.142m	8.166ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.370s	13.644ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	14.530s	2.122ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.160s	16.885ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.160s	16.885ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.190s	1.943ms	5	5	100.00
		rom_ctrl_csr_rw	14.020s	4.260ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.950s	1.593ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.000s	2.070ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.190s	1.943ms	5	5	100.00
		rom_ctrl_csr_rw	14.020s	4.260ms	20	20	100.00
		rom_ctrl_csr_aliasing	11.950s	1.593ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.000s	2.070ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.557m	111.092ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.773m	7.937ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.224m	12.276ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.773m	7.937ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.773m	7.937ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.773m	7.937ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	35.570s	14.913ms	46	50	92.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	35.570s	14.913ms	46	50	92.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	35.570s	14.913ms	46	50	92.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.224m	12.276ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
		rom_ctrl_kmac_err_chk	30.370s	13.644ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.441m	37.583ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.557m	111.092ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.773m	7.937ms	5	5	100.00
V2S		TOTAL			93	95	97.89
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.831h	36.034ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			477	500	95.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.86	97.16	93.27	97.88	86.67	99.01	98.19	98.84

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.3738342571
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b81d6bab-ecb4-4d7c-bc4a-aac8adaa4352
```
  - 1.rom_ctrl_stress_all_with_rand_reset.1480761160
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9793f9c7-234c-4d91-a156-173b128ada7a
```
  - ... and 9 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 9 failures:

Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

12.rom_ctrl_stress_all_with_rand_reset.3478025283
Line 223, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10103396583 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3f554b
  UVM_INFO @ 10103396583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.rom_ctrl_stress_all_with_rand_reset.2023220943
Line 222, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10107036357 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xc6840914
  UVM_INFO @ 10107036357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_smoke has 4 failures.

21.rom_ctrl_smoke.1848570378
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10007459021 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xc11bacb7
  UVM_INFO @ 10007459021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.rom_ctrl_smoke.1328984965
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10006459414 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x8f9156cf
  UVM_INFO @ 10006459414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all has 1 failures.

21.rom_ctrl_stress_all.3848991311
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10009644107 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x9a936097
  UVM_INFO @ 10009644107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 21.rom_ctrl_corrupt_sig_fatal_chk.2958493313
    Line 238, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 40.rom_ctrl_corrupt_sig_fatal_chk.2374897511
    Line 235, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/40.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 2855211594 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 2855211594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 49.rom_ctrl_kmac_err_chk.1627442236
    Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/49.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 2768119435 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 2768119435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```