f600eccc2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 42.460s | 41.967ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 18.170s | 4.251ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 14.940s | 1.841ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.120s | 26.342ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 13.760s | 3.331ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 15.440s | 7.609ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 14.940s | 1.841ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 13.760s | 3.331ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 11.510s | 5.045ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.380s | 4.066ms | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 18.080s | 8.671ms | 50 | 50 | 100.00 |
V2 | stress_all | rom_ctrl_stress_all | 1.869m | 38.977ms | 50 | 50 | 100.00 |
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 35.230s | 16.742ms | 50 | 50 | 100.00 |
V2 | alert_test | rom_ctrl_alert_test | 17.750s | 4.352ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 19.770s | 5.769ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 19.770s | 5.769ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 18.170s | 4.251ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 14.940s | 1.841ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 13.760s | 3.331ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 17.400s | 4.112ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 18.170s | 4.251ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 14.940s | 1.841ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 13.760s | 3.331ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 17.400s | 4.112ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 240 | 240 | 100.00 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 6.592m | 68.887ms | 19 | 20 | 95.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 1.843m | 240.609us | 5 | 5 | 100.00 |
rom_ctrl_tl_intg_err | 1.412m | 2.333ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.843m | 240.609us | 5 | 5 | 100.00 |
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.843m | 240.609us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.843m | 240.609us | 5 | 5 | 100.00 |
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 42.460s | 41.967ms | 50 | 50 | 100.00 |
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 42.460s | 41.967ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 42.460s | 41.967ms | 50 | 50 | 100.00 |
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.412m | 2.333ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
rom_ctrl_kmac_err_chk | 35.230s | 16.742ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 8.327m | 201.193ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 6.592m | 68.887ms | 19 | 20 | 95.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.843m | 240.609us | 5 | 5 | 100.00 |
V2S | TOTAL | 94 | 95 | 98.95 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 1.999h | 137.775ms | 36 | 50 | 72.00 |
V3 | TOTAL | 36 | 50 | 72.00 | |||
TOTAL | 485 | 500 | 97.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 6 | 6 | 6 | 100.00 |
V2S | 4 | 4 | 3 | 75.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.60 | 97.11 | 93.12 | 97.88 | 100.00 | 98.69 | 98.04 | 98.38 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 12 failures:
3.rom_ctrl_stress_all_with_rand_reset.2807389207
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1cb3065a-3172-4dce-a7f2-6285f6a3a286
4.rom_ctrl_stress_all_with_rand_reset.3551279641
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1c654318-572a-4e64-b62b-4be8fdc3c6f0
... and 10 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=*
has 2 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
3.rom_ctrl_passthru_mem_tl_intg_err.4004689370
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10008522104 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5686800c
UVM_INFO @ 10008522104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
34.rom_ctrl_stress_all_with_rand_reset.3113750933
Line 444, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 298631629644 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x539c9839
UVM_INFO @ 298631629644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked
has 1 failures:
5.rom_ctrl_stress_all_with_rand_reset.2530406980
Line 501, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 600194522038 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 600194522038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---