ROM_CTRL Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 39.210s 16.372ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 19.270s 3.436ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 16.700s 2.472ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 12.520s 5.253ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 10.430s 1.036ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 18.180s 8.545ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 16.700s 2.472ms 20 20 100.00
rom_ctrl_csr_aliasing 10.430s 1.036ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 14.540s 1.815ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 12.790s 4.083ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 17.220s 8.226ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.845m 12.628ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 33.390s 38.559ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 16.390s 12.029ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 18.660s 2.082ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 18.660s 2.082ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 19.270s 3.436ms 5 5 100.00
rom_ctrl_csr_rw 16.700s 2.472ms 20 20 100.00
rom_ctrl_csr_aliasing 10.430s 1.036ms 5 5 100.00
rom_ctrl_same_csr_outstanding 17.210s 1.947ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 19.270s 3.436ms 5 5 100.00
rom_ctrl_csr_rw 16.700s 2.472ms 20 20 100.00
rom_ctrl_csr_aliasing 10.430s 1.036ms 5 5 100.00
rom_ctrl_same_csr_outstanding 17.210s 1.947ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 7.361m 44.067ms 19 20 95.00
V2S tl_intg_err rom_ctrl_sec_cm 1.971m 2.779ms 5 5 100.00
rom_ctrl_tl_intg_err 1.383m 3.407ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.971m 2.779ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.971m 2.779ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.971m 2.779ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 39.210s 16.372ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 39.210s 16.372ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 39.210s 16.372ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.383m 3.407ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
rom_ctrl_kmac_err_chk 33.390s 38.559ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 9.719m 61.625ms 47 50 94.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 7.361m 44.067ms 19 20 95.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.971m 2.779ms 5 5 100.00
V2S TOTAL 91 95 95.79
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.908h 64.549ms 36 50 72.00
V3 TOTAL 36 50 72.00
TOTAL 482 500 96.40

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 2 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.54 97.11 92.83 97.88 100.00 98.69 97.89 98.38

Failure Buckets

Past Results