ROM_CTRL/32KB Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.436m	8.624ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	20.410s	2.172ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.650s	1.930ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.400s	1.313ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.560s	30.101ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.530s	9.397ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.650s	1.930ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.560s	30.101ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.020s	991.691us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.400s	5.179ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	35.310s	17.082ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	4.018m	100.361ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.192m	8.488ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	33.930s	4.067ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.690s	19.611ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.690s	19.611ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	20.410s	2.172ms	5	5	100.00
		rom_ctrl_csr_rw	15.650s	1.930ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.560s	30.101ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.090s	2.061ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	20.410s	2.172ms	5	5	100.00
		rom_ctrl_csr_rw	15.650s	1.930ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.560s	30.101ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.090s	2.061ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.751m	178.720ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.152m	14.331ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.320m	7.474ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.152m	14.331ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.152m	14.331ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.152m	14.331ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.436m	8.624ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.436m	8.624ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.436m	8.624ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.320m	7.474ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.192m	8.488ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	20.691m	472.054ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.751m	178.720ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.152m	14.331ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.485h	24.180ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.97	93.25	97.88	100.00	99.01	97.89	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 28 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.40515907821850435151922137239936410912781340203697602675608531601975131204481
    Line 304, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13876270207 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13876270207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rom_ctrl_stress_all_with_rand_reset.102376123374757163099956602803171027493903282934486186202866451805079893280747
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1021431107 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1021431107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.67998224294613943327823730687547423427020031167339013058272523496733800541488
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003580947 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd712a797
  UVM_INFO @ 10003580947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rom_ctrl_stress_all_with_rand_reset.17614460928373012372658372477921463683407520877287280115939426812495516301749
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10429217757 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfb83fa4
  UVM_INFO @ 10429217757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 33.rom_ctrl_stress_all_with_rand_reset.106597107598748692639645240357741227065055804194290245008311006470318301184992
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/33.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b6f4f3fc-ba64-4e98-9f46-7fe24601d72c
```
  - 35.rom_ctrl_stress_all_with_rand_reset.31839432445754176174031624159257145118157327504630682395922783980540555429895
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/35.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:adb495a4-3f22-4237-a95c-ae8e0b04ab34
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_smoke has 1 failures.
  - 4.rom_ctrl_smoke.19502090959599755383802853047377632183080063913503564438188368063530893228337
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 40016301542 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x553a3f34
  UVM_INFO @ 40016301542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_stress_all has 1 failures.
  - 14.rom_ctrl_stress_all.24615877085800632744330741981975063613330230163717064124259968356541797010419
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40119737842 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x910bbf27
  UVM_INFO @ 40119737842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c187a82ee8`