ROM_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.460s	3.423ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.480s	2.029ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.800s	4.145ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.350s	1.701ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.320s	4.275ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.140s	11.254ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.800s	4.145ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.320s	4.275ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.000s	1.916ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.990s	2.228ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.590s	15.634ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.801m	12.020ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.210s	8.827ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.380s	4.332ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.290s	10.063ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.290s	10.063ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.480s	2.029ms	5	5	100.00
		rom_ctrl_csr_rw	15.800s	4.145ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.320s	4.275ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.640s	26.393ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.480s	2.029ms	5	5	100.00
		rom_ctrl_csr_rw	15.800s	4.145ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.320s	4.275ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.640s	26.393ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.545m	44.472ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.821m	6.386ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.334m	17.187ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.821m	6.386ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.821m	6.386ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.821m	6.386ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.460s	3.423ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.460s	3.423ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.460s	3.423ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.334m	17.187ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.210s	8.827ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	6.975m	86.877ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.545m	44.472ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.821m	6.386ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.743h	150.444ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			463	500	92.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	97.04	92.80	97.88	100.00	98.69	97.89	98.84

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.72824679323312194306253352726767760593326861246567786415017644541807963501335
    Line 367, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28382343926 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28382343926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.75455224876094512932447566707534601731978205355682362376780477381986963677863
    Line 308, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11521544262 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11521544262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 14.rom_ctrl_stress_all_with_rand_reset.105709088191979228608637589074254786351821962528634955502569225319432448538755
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:535502ae-be72-406b-be18-6f3966050b52
```
  - 22.rom_ctrl_stress_all_with_rand_reset.16175360818701728367336758446484912885286289888931664947637777770214624555624
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f9760774-e3d2-49b2-82a5-b1b8b7ef37e0
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.rom_ctrl_stress_all_with_rand_reset.49119576606802480119886155944666120114161852028742054734746629832139103355109
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10016037766 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3eec646d
  UVM_INFO @ 10016037766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `36c168c253`