ROM_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.550s	28.392ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.870s	2.187ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.900s	4.147ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.980s	3.926ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.930s	743.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.370s	6.594ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.900s	4.147ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.930s	743.475us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.880s	7.572ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.860s	9.854ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	19.060s	30.955ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.885m	14.393ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.950s	16.948ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.870s	8.533ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.700s	2.146ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.700s	2.146ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.870s	2.187ms	5	5	100.00
		rom_ctrl_csr_rw	15.900s	4.147ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.930s	743.475us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.960s	9.553ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.870s	2.187ms	5	5	100.00
		rom_ctrl_csr_rw	15.900s	4.147ms	20	20	100.00
		rom_ctrl_csr_aliasing	8.930s	743.475us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.960s	9.553ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.685m	12.570ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.837m	2.182ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.337m	1.939ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.837m	2.182ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.837m	2.182ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.837m	2.182ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.550s	28.392ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.550s	28.392ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.550s	28.392ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.337m	1.939ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.950s	16.948ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.063m	214.891ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.685m	12.570ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.837m	2.182ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.426h	73.486ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.43	97.04	92.65	97.88	100.00	98.37	97.89	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.70444148074196300714682981359391387255692304115884664670498133738920691375855
    Line 315, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6908901963 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6908901963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rom_ctrl_stress_all_with_rand_reset.68681024490289268285762222997552640147918271996747146847720940343447588265360
    Line 277, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8037554234 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8037554234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.49763551335753778470814113549191904624800989579071453696046565515971534860967
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cc78cfe8-1df6-415a-9ed4-ab0a52945e5c
```
  - 10.rom_ctrl_stress_all_with_rand_reset.41229683093382166769128116626534656785847551205345135174176780703158502671388
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f3a0672a-0cf2-4214-b5e6-66f33a50ef4b
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.87609330176634168970570938808232310811725524872593159126041637724441894833408
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11991802573 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3b931fe9
  UVM_INFO @ 11991802573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.rom_ctrl_stress_all_with_rand_reset.19505249269787676218509137201442969452795878441925440762296120662695611119022
    Line 678, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 782595576279 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 782595576279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c30684b3ca`