ROM_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 42.550s 28.392ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 19.870s 2.187ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 15.900s 4.147ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 15.980s 3.926ms 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.930s 743.475us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 15.370s 6.594ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 15.900s 4.147ms 20 20 100.00
rom_ctrl_csr_aliasing 8.930s 743.475us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 15.880s 7.572ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 13.860s 9.854ms 5 5 100.00
V1 TOTAL 115 115 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 19.060s 30.955ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 1.885m 14.393ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 34.950s 16.948ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 16.870s 8.533ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 19.700s 2.146ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 19.700s 2.146ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 19.870s 2.187ms 5 5 100.00
rom_ctrl_csr_rw 15.900s 4.147ms 20 20 100.00
rom_ctrl_csr_aliasing 8.930s 743.475us 5 5 100.00
rom_ctrl_same_csr_outstanding 15.960s 9.553ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 19.870s 2.187ms 5 5 100.00
rom_ctrl_csr_rw 15.900s 4.147ms 20 20 100.00
rom_ctrl_csr_aliasing 8.930s 743.475us 5 5 100.00
rom_ctrl_same_csr_outstanding 15.960s 9.553ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 1.685m 12.570ms 20 20 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.837m 2.182ms 5 5 100.00
rom_ctrl_tl_intg_err 1.337m 1.939ms 20 20 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.837m 2.182ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.837m 2.182ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.837m 2.182ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 42.550s 28.392ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 42.550s 28.392ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 42.550s 28.392ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.337m 1.939ms 20 20 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
rom_ctrl_kmac_err_chk 34.950s 16.948ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 9.063m 214.891ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 1.685m 12.570ms 20 20 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.837m 2.182ms 5 5 100.00
V2S TOTAL 95 95 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.426h 73.486ms 19 50 38.00
V3 TOTAL 19 50 38.00
TOTAL 469 500 93.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.43 97.04 92.65 97.88 100.00 98.37 97.89 98.14

Failure Buckets

Past Results